Verilog 简易寄存器

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最新推荐文章于 2024-04-23 10:32:01 发布

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本文链接：https://blog.csdn.net/weixin_58196051/article/details/127655742

版权

寄存器，长版

寄存器，简短版

仿真 tp

约束（COE2020）（板不一样的不要用这个约束）

寄存器，长版

//
//
//创建日期：2022/10/16 21:37:00
//设计名称：寄存器堆
//课程名称：regfile
//说明：
// 实现 32 个寄存器， 其中 0 号寄存器读出的值恒为 0，
// 寄存器堆为异步读同步写， 
// 共有 1 个写端口和 2 个读端口
//依赖项：
//      
//版次：
//版本0.01-文件已创建
//其他注释：
//

module regfile(
input clk,  // 时钟
input wen,  // 写使能
input [4 :0] raddr1,    // 读地址1
input [4 :0] raddr2,    // 读地址2
input [4 :0] waddr,     // 写地址
input [31:0] wdata,     // 写数据
output reg [31:0] rdata1,   // 读到的数据1
output reg [31:0] rdata2,   // 读到的数据2
input [4 :0] test_addr,     // 测试读端口
output reg [31:0] test_data // 测试输出
); 
reg [31:0] rf[31:0];  // 定义32个32位的寄存器
always @(posedge clk) // 时钟上升沿
begin
    if (wen)    // 如果写使能wen为1则写入寄存器
        begin
           rf[waddr] <= wdata;
        end
end

//读端口 1
always @(*)
begin
    case (raddr1)
        5'd1 : rdata1 <= rf[1];
        5'd2 : rdata1 <= rf[2];
        5'd3 : rdata1 <= rf[3];
        5'd4 : rdata1 <= rf[4];
        5'd5 : rdata1 <= rf[5];
        5'd6 : rdata1 <= rf[6];
        5'd7 : rdata1 <= rf[7];
        5'd8 : rdata1 <= rf[8];
        5'd9 : rdata1 <= rf[9];
        5'd10 : rdata1 <= rf[10];
        5'd11 : rdata1 <= rf[11];
        5'd12 : rdata1 <= rf[12];
        5'd13 : rdata1 <= rf[13];
        5'd14 : rdata1 <= rf[14];
        5'd15 : rdata1 <= rf[15];
        5'd16 : rdata1 <= rf[16];
        5'd17 : rdata1 <= rf[17];
        5'd18 : rdata1 <= rf[18];
        5'd19 : rdata1 <= rf[19];
        5'd20 : rdata1 <= rf[20];
        5'd21 : rdata1 <= rf[21];
        5'd22 : rdata1 <= rf[22];
        5'd23 : rdata1 <= rf[23];
        5'd24 : rdata1 <= rf[24];
        5'd25 : rdata1 <= rf[25];
        5'd26 : rdata1 <= rf[26];
        5'd27 : rdata1 <= rf[27];
        5'd28 : rdata1 <= rf[28];
        5'd29 : rdata1 <= rf[29];
        5'd30 : rdata1 <= rf[30];
        5'd31 : rdata1 <= rf[31];
        default: rdata1 <= 32'd0;
    endcase
end
//读端口 2
always @(*)
begin
    case (raddr2)
        5'd1 : rdata2 <= rf[1];
        5'd2 : rdata2 <= rf[2];
        5'd3 : rdata2 <= rf[3];
        5'd4 : rdata2 <= rf[4];
        5'd5 : rdata2 <= rf[5];
        5'd6 : rdata2 <= rf[6];
        5'd7 : rdata2 <= rf[7];
        5'd8 : rdata2 <= rf[8];
        5'd9 : rdata2 <= rf[9];
        5'd10 : rdata2 <= rf[10];
        5'd11 : rdata2 <= rf[11];
        5'd12 : rdata2 <= rf[12];
        5'd13 : rdata2 <= rf[13];
        5'd14 : rdata2 <= rf[14];
        5'd15 : rdata2 <= rf[15];
        5'd16 : rdata2 <= rf[16];
        5'd17 : rdata2 <= rf[17];
        5'd18 : rdata2 <= rf[18];
        5'd19 : rdata2 <= rf[19];
        5'd20 : rdata2 <= rf[20];
        5'd21 : rdata2 <= rf[21];
        5'd22 : rdata2 <= rf[22];
        5'd23 : rdata2 <= rf[23];
        5'd24 : rdata2 <= rf[24];
        5'd25 : rdata2 <= rf[25];
        5'd26 : rdata2 <= rf[26];
        5'd27 : rdata2 <= rf[27];
        5'd28 : rdata2 <= rf[28];
        5'd29 : rdata2 <= rf[29];
        5'd30 : rdata2 <= rf[30];
        5'd31 : rdata2 <= rf[31];
        default: rdata2 <= 32'd0;
    endcase
end
//测试读端口
always @(*)
begin
    case (test_addr)
        5'd1 : test_data <= rf[1];
        5'd2 : test_data <= rf[2];
        5'd3 : test_data <= rf[3];
        5'd4 : test_data <= rf[4];
        5'd5 : test_data <= rf[5];
        5'd6 : test_data <= rf[6];
        5'd7 : test_data <= rf[7];
        5'd8 : test_data <= rf[8];
        5'd9 : test_data <= rf[9];
        5'd10 : test_data <= rf[10];
        5'd11 : test_data <= rf[11];
        5'd12 : test_data <= rf[12];
        5'd13 : test_data <= rf[13];
        5'd14 : test_data <= rf[14];
        5'd15 : test_data <= rf[15];
        5'd16 : test_data <= rf[16];
        5'd17 : test_data <= rf[17];
        5'd18 : test_data <= rf[18];
        5'd19 : test_data <= rf[19];
        5'd20 : test_data <= rf[20];
        5'd21 : test_data <= rf[21];
        5'd22 : test_data <= rf[22];
        5'd23 : test_data <= rf[23];
        5'd24 : test_data <= rf[24];
        5'd25 : test_data <= rf[25];
        5'd26 : test_data <= rf[26];
        5'd27 : test_data <= rf[27];
        5'd28 : test_data <= rf[28];
        5'd29 : test_data <= rf[29];
        5'd30 : test_data <= rf[30];
        5'd31 : test_data <= rf[31];
        default: test_data <= 32'd0;
    endcase
end

endmodule

寄存器，简短版

//
//
//创建日期：2022/10/16 21:37:00
//设计名称：寄存器堆
//课程名称：regfile
//说明：
// 实现 32 个寄存器， 其中 0 号寄存器读出的值恒为 0，
// 寄存器堆为异步读同步写， 
// 共有 1 个写端口和 2 个读端口
//依赖项：
//      
//版次：
//版本0.01-文件已创建
//其他注释：
//

module regfile(
input clk,  // 时钟
input wen,  // 写使能
input [4 :0] raddr1,    // 读地址1
input [4 :0] raddr2,    // 读地址2
input [4 :0] waddr,     // 写地址
input [31:0] wdata,     // 写数据
output reg [31:0] rdata1,   // 读到的数据1
output reg [31:0] rdata2,   // 读到的数据2
input [4 :0] test_addr,     // 测试读端口
output reg [31:0] test_data // 测试输出
); 
reg [31:0] rf[31:0];  // 定义32个32位的寄存器
always @(posedge clk) // 时钟上升沿
begin
    if (wen)    // 如果写使能wen为1则写入寄存器
        begin
           rf[waddr] <= wdata;
        end
end

//读端口 1
always @(*)
begin
    if (raddr1==5'd0)
        rdata1 <= 32'd0;
    else
        rdata1 <= rf[raddr1];
end
//读端口 2
always @(*)
begin
    if (raddr2==5'd0)
        rdata2 <= 32'd0;
    else
        rdata2 <= rf[raddr2];
end
//测试读端口
always @(*)
begin
    if (test_addr==5'd0)
        test_data <= 32'd0;
    else
        test_data <= rf[test_addr];
end
endmodule

仿真 tp

`timescale 1ns / 1ps
module tb;
    reg clk;
	reg wen;
	reg [4 :0] raddr1; 
	reg [4 :0] raddr2;
	reg [4 :0] waddr;
	reg [31:0] wdata;
	reg [4 :0] test_addr;

    wire [31:0] rdata1;
	wire [31:0] rdata2;
	wire [31:0] test_data;
    regfile rf(
    .clk(clk),
    .wen(wen),
    .raddr1(raddr1),
    .raddr2(raddr2),
    .waddr(waddr),
    .wdata(wdata),
    .rdata1(rdata1),
    .rdata2(rdata2),
    .test_addr(test_addr),
    .test_data(test_data)
    );
 
    initial begin
        clk = 0;
        wen = 0;
        raddr1 = 0;
        raddr2 = 0;
		waddr = 0;
		wdata = 0;
		test_addr = 0;

        #10;
		waddr = 5'h1f;
		wdata = 32'h147af;
        #40;
        wen = 1'b1;
        #50;
        wen = 1'b0;
        

        #100;
        raddr1 = 5'h1f;
        #100;
        raddr2 = 5'h1f;
        #100;
        test_addr = 5'h1f;
        
    end
   always #5 clk = ~clk;
endmodule

约束（COE2020）（板不一样的不要用这个约束）

微动开关右边，第一个是写使能，第二第三个是控制读地址和写地址写数据的lcd屏输入

set_property PACKAGE_PIN AC19 [get_ports clk]
set_property PACKAGE_PIN AB21 [get_ports resetn]

set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports resetn]

#led
set_property PACKAGE_PIN U26 [get_ports led_wen]
set_property PACKAGE_PIN U25 [get_ports led_waddr]
set_property PACKAGE_PIN U24 [get_ports led_wdata]
set_property PACKAGE_PIN U22 [get_ports led_raddr1]
set_property PACKAGE_PIN V26 [get_ports led_raddr2]


set_property IOSTANDARD LVCMOS33 [get_ports led_wen1]
set_property IOSTANDARD LVCMOS33 [get_ports led_waddr]
set_property IOSTANDARD LVCMOS33 [get_ports led_wdata]
set_property IOSTANDARD LVCMOS33 [get_ports led_raddr1]
set_property IOSTANDARD LVCMOS33 [get_ports led_raddr2]
#lcd
set_property PACKAGE_PIN E5 [get_ports lcd_rst]
set_property PACKAGE_PIN G7 [get_ports lcd_cs]
set_property PACKAGE_PIN H7 [get_ports lcd_rs]
set_property PACKAGE_PIN E6 [get_ports lcd_wr]
set_property PACKAGE_PIN D5 [get_ports lcd_rd]
set_property PACKAGE_PIN J5 [get_ports lcd_bl_ctr]
set_property PACKAGE_PIN C4 [get_ports {lcd_data_io[0]}]
set_property PACKAGE_PIN C3 [get_ports {lcd_data_io[1]}]
set_property PACKAGE_PIN D4 [get_ports {lcd_data_io[2]}]
set_property PACKAGE_PIN D3 [get_ports {lcd_data_io[3]}]
set_property PACKAGE_PIN F5 [get_ports {lcd_data_io[4]}]
set_property PACKAGE_PIN G6 [get_ports {lcd_data_io[5]}]
set_property PACKAGE_PIN F4 [get_ports {lcd_data_io[6]}]
set_property PACKAGE_PIN E3 [get_ports {lcd_data_io[7]}]
set_property PACKAGE_PIN G5 [get_ports {lcd_data_io[8]}]
set_property PACKAGE_PIN H6 [get_ports {lcd_data_io[9]}]
set_property PACKAGE_PIN F2 [get_ports {lcd_data_io[10]}]
set_property PACKAGE_PIN F3 [get_ports {lcd_data_io[11]}]
set_property PACKAGE_PIN G4 [get_ports {lcd_data_io[12]}]
set_property PACKAGE_PIN G2 [get_ports {lcd_data_io[13]}]
set_property PACKAGE_PIN H4 [get_ports {lcd_data_io[14]}]
set_property PACKAGE_PIN H3 [get_ports {lcd_data_io[15]}]
set_property PACKAGE_PIN K6 [get_ports ct_int]
set_property PACKAGE_PIN J6 [get_ports ct_sda]
set_property PACKAGE_PIN L8 [get_ports ct_scl]
set_property PACKAGE_PIN K7 [get_ports ct_rstn]

set_property IOSTANDARD LVCMOS33 [get_ports lcd_rst]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_cs]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_rs]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_wr]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_rd]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_bl_ctr]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports ct_int]
set_property IOSTANDARD LVCMOS33 [get_ports ct_sda]
set_property IOSTANDARD LVCMOS33 [get_ports ct_scl]
set_property IOSTANDARD LVCMOS33 [get_ports ct_rstn]



set_property PACKAGE_PIN AE17 [get_ports wen]
set_property IOSTANDARD LVCMOS33 [get_ports wen]
set_property PACKAGE_PIN AF17 [get_ports {input_sel[1]}]
set_property PACKAGE_PIN AE18 [get_ports {input_sel[0]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {input_sel[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {input_sel[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports led_wen]