【FPGA】[Synth 8-5535] port ＜adc_clk_out＞ has illegal connections.

问题描述

[Synth 8-5535] port <adc_clk_out> has illegal connections. It is illegal to have a port connected to an input buffer and other components. The following are the port connections :
Input Buffer:
	Port I of instance clkin1_ibuf(IBUF) in module <ad9250_adc_pll_clk_wiz>
Other Components:
	Port WRCLK of instance \inst_fifo_gen/gconvfifo.rf/gbi.bi/v8_fifo.fblk/rst_val_asym.gextw_asym[1].inst_extd/gonep.inst_prim/gf36e2_inst.sngfifo36e2 (FIFO36E2) in module fifo_generator_v13_2_3

问题原因

因为生成的这个PLL的参考时钟前自带了IBUF，如下：

而PLL的输入时钟是由外部差分时钟输入后已经经过一个BUFG，造成BUF级联。

解决方法

修改PLL输入参考时钟自动插入的IBUF。