Verilog刷题-15-Vectorgates

最新推荐文章于 2024-09-30 13:22:45 发布

不知道叫啥好一点

最新推荐文章于 2024-09-30 13:22:45 发布

阅读量1.9k

点赞数

分类专栏： Verilog刷题文章标签： verilog

本文链接：https://blog.csdn.net/A_A666/article/details/107230619

版权

Verilog刷题专栏收录该内容

22 篇文章 30 订阅

订阅专栏

题目描述

文字描述
Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.
图示

说明：while a logical operation treats the entire vector as a boolean value (true = non-zero, false = zero) and produces a 1-bit output.

代码

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise = a|b;
    assign out_or_logical = (a>0)|(b>0);   // 不知道为什么 (a>3’b000)|(b>3‘b000)就不正确，怀疑是平台的问题
    // assign out_or_logical = a || b;    // 参考方案，我这里想复杂了
    assign out_not = {~b,~a};
endmodule