Verilog 练习 4级伪随机码发生器

 

 代码如下

//2121-11-2
//四级伪随机码发生器
module m_gen(clk,res,y);
input clk,res;
output y;

reg[3:0] d;
assign y=d[0];

always@(posedge clk or negedge res)
if(~res) begin 
d<=4'b1111;
end 
else begin 
	d[2:0]<=d[3:1];
	d[3]<=d[3]+d[0];
end 
endmodule 



//----testbench of m_gen-----
module m_gen_tb;
reg clk,res;
wire y;

m_gen m_gen(.clk(clk),.res(res),.y(y));

initial begin 
		clk<=0;res<=0;
		#17 res<=1;
		#600 $stop;
end 

always#5 clk=~clk;

endmodule

仿真结果如下

https://www.bilibili.com/video/BV1hX4y137Ph?p=4&spm_id_from=pageDriver