Verilog学习笔记 （二）伪随机序列产生器

Verilog和C语言 伪随机序列产生器

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下面用两种方式产生伪随机序列产生器

一、利用LFSR（线性反馈移位寄存器）

只要学习过数电知识的应该都不难理解上图时序逻辑电路 

module pn_gen(clk,n_rst,y);     //利用Verilog编写，在vivado仿真实现
input clk,n_rst;
output [7:0] y;

reg [7:0] LFSR,LFSR_next;
reg [7:0] Feedback;

always @(posedge clk)
begin
    if(!n_rst)
        LFSR = 8'b0000_0000;
    else
        LFSR = LFSR_next;
end

always @(LFSR)
begin
    Feedback = LFSR[7]^(~|LFSR[6:0]);  //根据上图移位寄存器
    LFSR_next[7] = LFSR[6];
    LFSR_next[6] = LFSR[5];
    LFSR_next[5] = LFSR[4];
    LFSR_next[4] = LFSR[3];
    LFSR_next[3] = LFSR[2];
    LFSR_next[2] = LFSR[1];
    LFSR_next[1] = LFSR[0];
    LFSR_next[0] = Feedback;
end
assign y = LFSR;
endmodule