VHDL实现8位十进制加法器

设计文件

module bcd_adder(
    input [3:0] A,
    input [3:0] B,
    input Cin,
    output reg [3:0] Sum,
    output reg Cout
);
    reg [4:0] temp;
    
    always @(A, B, Cin) begin
        temp = A + B + Cin;
        if(temp > 9) begin
            Sum = temp + 6;
            Cout = 1;
        end
        else begin
            Sum = temp;
            Cout = 0;
        end
    end
endmodule

module decimal_adder(
    input [7:0] A,
    input [7:0] B,
    output [7:0] Sum,
    output Cout
);
    wire [3:0] sum_low, sum_high;
    wire cout_low, cout_high;
    
    bcd_adder low_adder (
        .A(A[3:0]),
        .B(B[3:0]),
        .Cin(0),
        .Sum(sum_low),
        .Cout(cout_low)
    );
    
    bcd_adder high_adder (
        .A(A[7:4]),
        .B(B[7:4]),
        .Cin(cout_low),
        .Sum(sum_high),
        .Cout(cout_high)
    );
    
    assign Sum = {sum_high, su