一、软件介绍
1、Quartus II
该软件是Altera公司推出的综合性CPLD/FPGA开发软件,软件支持原理图、VHDL、VerilogHDL以及AHDL等多种设计输入形式,内嵌自有的综合器以及仿真器,可以完成从设计输入到硬件配置的完整PLD设计流程。
其下载连接如下:
https://www.intel.cn/content/www/cn/zh/content-details/653796/quartus-ii-handbook-version-13-1.html
2、ModelSim
其是Mentor公司的最优秀的HDL语言仿真软件,它能提供友好的仿真环境,是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术,编译仿真速度快,编译的代码与平台无关,便于保护IP核,个性化的图形界面和用户接口,为用户加快调错提供强有力的手段,是FPGA/ASIC设计的首选仿真软件。
其下载连接如下:
该软件ModelSim Student Edition 暂时不可在官网下载,可以自行在B站或者各大网站寻找资源进行下载使用。
二、三八译码器
3-8线译码器是一种全译码器(二进制译码器)。输入是3个脚(3位二进制代码),输出是8个脚(表示10进制,是根据输入的二进制数来输出。3位二进制代码共有8种组合,故输出是与这8种组合一一对应的8个输出信号)
我们以a、b、c作为输出,Y0 -- Y7作为输出,
当:
abc = 000 时,Y0 = 1,其余为0;
abc = 001 时,Y1 = 1,其余为0;
abc = 010 时,Y2 = 1,其余为0;
abc = 011 时,Y3 = 1,其余为0;
abc = 100 时,Y4 = 1,其余为0;
abc = 101 时,Y5 = 1,其余为0;
abc = 110 时,Y6 = 1,其余为0;
abc = 111 时,Y7 = 1,其余为0。
电路图、真值表
其电路图以及真值表如下图所示:
生成RTL
代码:
module Decoder_3to8 (
input [2:0] input_bits,
output [7:0] output_bits
);
assign output_bits[0] = (input_bits == 3'b000) ? 1'b1 : 1'b0;
assign output_bits[1] = (input_bits == 3'b001) ? 1'b1 : 1'b0;
assign output_bits[2] = (input_bits == 3'b010) ? 1'b1 : 1'b0;
assign output_bits[3] = (input_bits == 3'b011) ? 1'b1 : 1'b0;
assign output_bits[4] = (input_bits == 3'b100) ? 1'b1 : 1'b0;
assign output_bits[5] = (input_bits == 3'b101) ? 1'b1 : 1'b0;
assign output_bits[6] = (input_bits == 3'b110) ? 1'b1 : 1'b0;
assign output_bits[7] = (input_bits == 3'b111) ? 1'b1 : 1'b0;
endmodule
测试代码:
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to
// suit user's needs .Comments are provided in each section to help the user
// fill out necessary details.
// *****************************************************************************
// Generated on "12/16/2023 19:59:12"
// Verilog Test Bench template for design : Decoder_3to8
//
// Simulation tool : ModelSim (Verilog)
//
`timescale 1 ps/ 1 ps
module Decoder_3to8_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg [2:0] input_bits;
// wires
wire [7:0] output_bits;
// assign statements (if any)
Decoder_3to8 i1 (
// port map - connection between master ports and signals/registers
.input_bits(input_bits),
.output_bits(output_bits)
);
initial
begin
$display("Running testbench");
// Test case 1
input_bits = 3'b000;
#10;
if (output_bits !== 8'b00000001) $fatal("Test case 1 failed");
// Test case 2
input_bits = 3'b001;
#10;
if (output_bits !== 8'b00000010) $fatal("Test case 2 failed");
// Test case 3
input_bits = 3'b010;
#10;
if (output_bits !== 8'b00000100) $fatal("Test case 3 failed");
// Test case 4
input_bits = 3'b011;
#10;
if (output_bits !== 8'b00001000) $fatal("Test case 4 failed");
// Test case 5
input_bits = 3'b100;
#10;
if (output_bits !== 8'b00010000) $fatal("Test case 5 failed");
// Test case 6
input_bits = 3'b101;
#10;
if (output_bits !== 8'b00100000) $fatal("Test case 6 failed");
// Test case 7
input_bits = 3'b110;
#10;
if (output_bits !== 8'b01000000) $fatal("Test case 7 failed");
// Test case 8
input_bits = 3'b111;
#10;
if (output_bits !== 8'b10000000) $fatal("Test case 8 failed");
end
always
begin
@eachvec;
end
endmodule
波形图:
后期建议大家多加强软件运用,环境的调试,防止因为软件设置等其他原因造成无法生成图像或者波形图之类的问题出现,同时也是为了后续实验能更快速完成。