VHDL10：VHDL实现运算符重载并仿真，vhdl下包（package）的使用

目录

1. 示例说明

2. 创建在EG8工程

3. 在EG8工程下创建ReOperator.vhd文件

4. 在EG8工程下创建EG8.vhd文件

5. 工程编译结果

6. 功能仿真结果

7. 文件调用说明

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1. 示例说明

本例引入了包的概念，在ReOperator文件中创建包，并在包下创建了两个函数bit_to_int和“+”运算符重载。在EG8.vhd文件下通过引入包后再引入相关函数做操作。

工程文件关系如下：

 

2. 创建在EG8工程

 

3. 在EG8工程下创建ReOperator.vhd文件

 

ReOperator.vhd源码文件：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

package ReOperator is

-- 包头（包说明）

         subtype short is integer range 0 to 65535;

         subtype int4 is integer range 0 to 16;

         subtype int8 is integer range 0 to 255;

        

         --以下均为函数头，具体定义见包体

         function bit_to_int (in1: bit_vector) return integer;

         function "+" (in1, in2: bit_vector) return integer;

end ReOperator;

package body ReOperator is -- 包体，由关键字package body标识

         -- 函数 bit_to_int将位向量转化为十进制整数值

         function bit_to_int (in1: bit_vector) return integer is

                            alias v1: bit_vector(in1' length-1 downto 0) is in1;

                            variable inpv: bit_vector(in1' length-1 downto 0);

                            variable SUM: integer := 0;

                            variable negative: boolean := false;

                           

                   begin       

                            inpv := in1;

                            if v1(v1' length-1) = '1' then

                                     for i in v1' length-1 downto 0 loop

                                               inpv(i) := not inpv(i);

                                     end loop;

                            lp1:

                                     for i in 0 to v1' length-1 loop

                                               if inpv(i) = '1' then

                                                        inpv(i) := '0';

                                               else

                                                        inpv(i) := '1';

                                                        exit lp1;

                                               end if;

                                     end loop;

                            negative := true;

                            end if;

                            for i in v1' length-1 downto 0 loop

                                     if inpv(i) = '1' then SUM := SUM+2**i;

                                     end if;

                            end loop;

                            if negative then return (0-SUM);

                            else return SUM;

                            end if;

         end bit_to_int;

         -- 重载函数  “+” 将两个位向量相加，得到相应的整数值

         function "+" (in1, in2:bit_vector) return integer is

         begin

                   -- 用到了前面定义的函数bit_to_int,将两个位向量先分别转化为整数，然后再相加

                   return (bit_to_int(in1) + bit_to_int(in2));

         end "+";

end ReOperator;

        

4. 在EG8工程下创建EG8.vhd文件

 

EG8.vhd源码文件：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY work;

use work.ReOperator.all;

entity EG8 is --带控制端口的加法器，输入输出为位向量

         port(

                   in1 : in bit_vector(15 downto 0);

                   in2 : in bit_vector(15 downto 0);

                   cnt1 : in bit;

                   pout : out integer

         );

end EG8;

architecture func of EG8 is

begin

         process(cnt1)            -- 带有信号敏感表的进程，敏感信号为cnt1

         begin                          

                   if(cnt1 = '1') then pout <= in1 + in2; -- 调用“+”运算符重载

                   end if;

         end process;

end func;

5. 工程编译结果

 

6. 功能仿真结果

 

7. 文件调用说明