FPGA学习笔记 -- 流水灯

设计四个led灯进行循环闪烁

 

module water_led
#(parameter CNT_MAX = 25'd24_999_999) //这个计数可延迟0.5s
(
	input wire sys_clk,
	input wire res_n,
	
	output wire [3:0] led_out
);

reg [24:0] cnt;
reg cnt_flag;
reg [3:0] led_out_flag;

always@(posedge sys_clk or negedge res_n) // 定义计数延时
	if(res_n == 1'b0)
		cnt <= 25'd0;
	else if(cnt == CNT_MAX)
		cnt <= 25'd0;
	else
		cnt <= cnt + 25'd1;
		
always@(posedge sys_clk or negedge res_n) // 定义计数标志
	if(res_n == 1'b0)
		cnt_flag <= 1'b0;
	else if(cnt == CNT_MAX - 25'd1)
		cnt_flag <= 1'b1;
	else
		cnt_flag <= 1'b0;

always@(posedge sys_clk or negedge res_n) // 定义led灯的状态
	if(res_n == 1'b0)
		led_out_flag <= 4'b0001;
	else if((led_out_flag == 4'b1000)&&(cnt_flag == 1'b1))
		led_out_flag <= 4'b0001;
	else if(cnt_flag == 1'b1)
	led_out_flag <= led_out_flag << 1; //逻辑移位，其后补零，不符合预期，verilog中没有循环移位的表示，所以需要自定义循环移位 
		
assign led_out = ~led_out_flag; //由于移位是其后补零，所以直接将整体取反进行赋值，最后转过来即可
endmodule

`timescale 1ns/1ns
module tb_water_led();

reg sys_clk;
reg res_n;

wire [3:0] led_out;

initial
	begin
		sys_clk = 1'b1;
		res_n <= 1'b0;
		#20
		res_n <= 1'b1;
	end

always #10 sys_clk = ~sys_clk;

water_led
#(.CNT_MAX(25'd24))
water_led_1  // 注意实例化名称在参数之后
(
	.sys_clk(sys_clk),
	.res_n(res_n),
	
	.led_out(led_out)
);

endmodule

 呼吸灯效果

 按以往单片机及硬件电路所学，当给灯加的电压越高灯就越亮，但实际芯片输出的电压是固定的，所以需要以另一种形式来模拟电压的高低，这里可以采用类似PWM波的形式，以周期的大小来作为电压的高低，这是利用了人的视觉残留效果，停留时间越长感官越强。

 设呼吸时间为1s，将其再分为1ms呼吸效果较好，这里系统时钟频率为50MHZ，1个时钟周期为20ns，这里低电平为点亮。下图展示为灯由暗到亮的过程，由亮到暗的过程只需要将led_out进行取反即可

 

module breath_led
#(
	parameter cnt_1us_max = 6'd49,
	parameter cnt_1ms_max = 10'd999,
	parameter cnt_1s_max = 10'd999
)
(
	input wire sys_clk,
	input wire res_n,
	
	output reg led_out
);

reg [5:0] cnt_1us;
reg [9:0] cnt_1ms;
reg [9:0] cnt_1s;
reg cnt_en;

always@(posedge sys_clk or negedge res_n)
	if(res_n == 1'b0)
		cnt_1us <= 6'd0;
	else if(cnt_1us == cnt_1us_max)
		cnt_1us <= 6'd0;
	else
		cnt_1us <= cnt_1us + 6'd1;

always@(posedge sys_clk or negedge res_n)
	if(res_n == 1'b0)
		cnt_1ms <= 10'd0;
	else if((cnt_1ms == cnt_1ms_max)&&(cnt_1us == cnt_1us_max))
		cnt_1ms <= 10'd0;
	else if(cnt_1us == cnt_1us_max)
		cnt_1ms <= cnt_1ms + 10'd1;
	else
		cnt_1ms <= cnt_1ms;

always@(posedge sys_clk or negedge res_n)
	if(res_n == 1'b0)
		cnt_1s <= 10'd0;
	else if((cnt_1s == cnt_1s_max)&&(cnt_1ms == cnt_1ms_max)&&(cnt_1us == cnt_1us_max))
		cnt_1s <= 10'd0;
	else if((cnt_1ms == cnt_1ms_max)&&(cnt_1us == cnt_1us_max))
		cnt_1s <= cnt_1s + 10'd1;
	else
		cnt_1s <= cnt_1s;

always@(posedge sys_clk or negedge res_n) 
	if(res_n == 1'b0)
		cnt_en <= 1'b0; //信号标志，初始低电平，每隔1s翻转标志灯是由亮转暗或由按转亮两种状态
	else if((cnt_1s == cnt_1s_max)&&(cnt_1ms == cnt_1ms_max)&&(cnt_1us == cnt_1us_max))
		cnt_en <= ~cnt_en;
	else
		cnt_en <= cnt_en;

always@(posedge sys_clk or negedge res_n)
	if(res_n == 1'b0)
		led_out <= 1'b1;
	else if((cnt_en == 1'b0)&&(cnt_1ms <= cnt_1s)
				||(cnt_en == 1'b1)&&(cnt_1ms > cnt_1s))
		led_out <= 1'b0;
	else
		led_out <= 1'b1;
		
endmodule

 

`timescale 1ns/1ns

module tb_breath_led();

reg sys_clk;
reg res_n;

wire led_out;

initial
	begin
		sys_clk = 1'b1;
		res_n <= 1'b0;
		#30
		res_n <= 1'b1;
	end

always #10 sys_clk = ~sys_clk;

breath_led
#(
	.cnt_1us_max(6'd10),
	.cnt_1ms_max(10'd30),
	.cnt_1s_max(10'd30)
)
breath_led_1
(
	.sys_clk(sys_clk),
	.res_n(res_n),
	
	.led_out(led_out)
);
	
endmodule