module shift_register(out,reset,load,clk,data,select);
output [7:0]out;
input clk,load,reset;
input [7:0]data;
input [1:0]select;
reg temp_out;
reg temp_cin;
reg [7:0]out;
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
out=0;
temp_cin=1;
end
elseif(load)
begin
out=data;
temp_cin=1;
end
else
begin
case(select[1:0])2'b00:out<={out[6:0],out[7]};2'b01:
begin
temp_out=out[7];
out={out[6:0],temp_cin};
temp_cin=temp_out;
end
2'b10:out<={out[0],out[7:1]};2'b11:
begin
temp_out=out[0];
out={temp_cin,out[7:1]};
temp_cin=temp_out;
end
default:
out<=8'bxx;
endcase
end
end
Endmodule