questasim/modelsim独立仿真vivado ddr3控制器（mig）

玲玲一

已于 2024-03-26 08:41:09 修改

阅读量2.6k

点赞数 27

文章标签： fpga开发

于 2024-03-24 22:35:24 首次发布

本文链接：https://blog.csdn.net/weixin_48027403/article/details/136985890

版权

1.使用场合介绍

当工程中使用DDR做数据缓存时，使用vivado默认仿真器进行功能仿真时速率特别慢，而使用vivado和questasim联合仿真选项虽然能加速仿真（相当于从vivado跳转到questasim进行仿真），但是调试过程中每次修改代码都需要在vivado工具上修改并编译后再跳转到questasim进行波形仿真，流程比较麻烦。本文通过将vivado仿真ddr3控制器所需要的仿真文件扣出来到questasim中进行独立编译仿真。

2.使用vivado联合questasim仿真

为了了解仿真DDR3所需要的文件以及编译流程，先通过vivado跳转到questasim仿真查看编译了哪些文件。

2.1搭建仿真环境

2.1.1导出mig仿真例程

根据自己板子的ddr3芯片型号和使用需求生成mig,本文将mig ip核生成名为ddr3，勾选AXI4 Interface选项,在source框右击ddr3,选择Open Ip Example Design...选项，创建仿真工程ddr3_ex。

仿真工程生成好后找到ddr3_ex文件夹路径下imports文件夹，导入ddr3_model.sv,ddr3_model_parameters.vh,wiredly.v到自己工程目录下，并将sim_tb_top.v中的example_top换成自己需要仿真的顶层文件。最终如下图所示

2.2.2设置vivado仿真工具

点击Tools->setting

修改如下设置

点击Run Simulation跳转到questasim进行仿真，如下图所示

仿真波形

2.2.3 查看仿真流程

进入工程路径下XX.sim->sim_1->behav->questa，有三个脚本可执行文件compile.bat,elaborate.bat和simulate.bat。分别代表仿真的三个步骤：综合，优化，执行仿真。

compile.bat：综合脚本，对源文件进行综合。脚本调用了DDR_AXI_tb_compile.do

@echo off
REM ****************************************************************************
REM Vivado (TM) v2021.1 (64-bit)
REM
REM Filename    : compile.bat
REM Simulator   : Mentor Graphics Questa Advanced Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Sun Mar 24 21:40:16 +0800 2024
REM SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
REM
REM IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
REM
REM usage: compile.bat
REM
REM ****************************************************************************
set bin_path=D:\\questa202101\\win64
call %bin_path%/vsim  -c -do "do {DDR_AXI_tb_compile.do}" -l compile.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
:END
exit 1
:SUCCESS
exit 0

DDR_AXI_tb_compile.do

包含Mig控制器仿真需要的所有源文件路径，将所有路径下的源文件拷贝出来，后期使用questasim独立综合使用。

######################################################################
#
# File name : DDR_AXI_tb_compile.do
# Created on: Sun Mar 24 21:40:16 +0800 2024
#
# Auto generated by Vivado for 'behavioral' simulation
#
######################################################################
D:\\questa202101\\win64\\vlib questa_lib/work
D:\\questa202101\\win64\\vlib questa_lib/msim

D:\\questa202101\\win64\\vlib questa_lib/msim/xil_defaultlib

D:\\questa202101\\win64\\vmap xil_defaultlib questa_lib/msim/xil_defaultlib

D:\\questa202101\\win64\\vlog  -incr -mfcu -work xil_defaultlib  "+incdir+../../../../../imports" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_addr_decode.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_read.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg_bank.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_top.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_write.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_ar_channel.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_arbiter.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_fsm.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_simple_fifo.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_upsizer.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_a_upsizer.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_and.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_latch_and.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_latch_or.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_or.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_command_fifo.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator_sel.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator_sel_static.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_r_upsizer.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_w_upsizer.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3_mig_sim.v" \
"../../../../project_1.gen/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3.v" \
"../../../../../src/fdma_test.v" \
"../../../../../src/signal_sync.v" \
"../../../../../src/uiFDMA.v" \
"../../../../../imports/wiredly.v" \

D:\\questa202101\\win64\\vlog  -incr -mfcu -sv -work xil_defaultlib  "+incdir+../../../../../imports" \
"../../../../../imports/ddr3_model.sv" \

D:\\questa202101\\win64\\vlog  -incr -mfcu -work xil_defaultlib  "+incdir+../../../../../imports" \
"../../../../../tb/DDR_AXI_tb.v" \

# compile glbl module
D:\\questa202101\\win64\\vlog -work xil_defaultlib "glbl.v"

quit -force

elaborate.bat：优化

@echo off
REM ****************************************************************************
REM Vivado (TM) v2021.1 (64-bit)
REM
REM Filename    : elaborate.bat
REM Simulator   : Mentor Graphics Questa Advanced Simulator
REM Description : Script for elaborating the compiled design
REM
REM Generated by Vivado on Sun Mar 24 21:40:34 +0800 2024
REM SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
REM
REM IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
REM
REM usage: elaborate.bat
REM
REM ****************************************************************************
set bin_path=D:\\questa202101\\win64
call %bin_path%/vsim  -c -do "do {DDR_AXI_tb_elaborate.do}" -l elaborate.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
:END
exit 1
:SUCCESS
exit 0

DDR_AXI_tb_elaborate.do

######################################################################
#
# File name : DDR_AXI_tb_elaborate.do
# Created on: Sun Mar 24 21:40:34 +0800 2024
#
# Auto generated by Vivado for 'behavioral' simulation
#
######################################################################
D:\\questa202101\\win64\\vopt +acc=npr -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -work xil_defaultlib xil_defaultlib.DDR_AXI_tb xil_defaultlib.glbl -o DDR_AXI_tb_opt

quit -force

simulate.bat：启动仿真

@echo off
REM ****************************************************************************
REM Vivado (TM) v2021.1 (64-bit)
REM
REM Filename    : simulate.bat
REM Simulator   : Mentor Graphics Questa Advanced Simulator
REM Description : Script for simulating the design by launching the simulator
REM
REM Generated by Vivado on Sun Mar 24 21:40:47 +0800 2024
REM SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
REM
REM IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
REM
REM usage: simulate.bat
REM
REM ****************************************************************************
set bin_path=D:\\questa202101\\win64
call %bin_path%/vsim   -do "do {DDR_AXI_tb_simulate.do}" -l simulate.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
:END
exit 1
:SUCCESS
exit 0

DDR_AXI_tb_simulate.do

######################################################################
#
# File name : DDR_AXI_tb_simulate.do
# Created on: Sun Mar 24 21:40:47 +0800 2024
#
# Auto generated by Vivado for 'behavioral' simulation
#
######################################################################
vsim -lib xil_defaultlib DDR_AXI_tb_opt

set NumericStdNoWarnings 1
set StdArithNoWarnings 1

do {DDR_AXI_tb_wave.do}

view wave
view structure
view signals

do {DDR_AXI_tb.udo}

run 1000ns

3.移植到questasim进行独立仿真

参照上面仿真步骤以及之前博文（使用tcl脚本在questasim中仿真vivado工程）中questasim脚本仿真流程，编写仿真脚本

sim_axi_ddr.tcl


set system_name      DDR_MIG
set TOP_LEVEL_NAME   DDR_AXI_tb

vlib   questa_lib
vlib ./questa_lib/work
vlib ./questa_lib/msim
vlib ./questa_lib/msim/work
# compile system, only need to run once (without IP and src changes)
alias build {
  # compile ddr3 simulation model
   vlog  -mfcu -work work -f  filelist.f
   vlog  -mfcu -work work   ../../../src/axi_ddr/imports/wiredly.v
   vlog  -mfcu -sv -work work   ../../../src/axi_ddr/imports/ddr3_model.sv
   # compile glbl module
   vlog -work work "glbl.v"
   # compile user module
   vlog -incr -mfcu -work work ../../../src/axi_ddr/*.v
   vlog  -incr -mfcu -work work DDR_AXI_tb.v
}
alias elab_ddr3 {
  vopt +acc=npr -L work -L unisims_ver -L unimacro_ver -L secureip -L xpm -work work work.DDR_AXI_tb work.glbl -o DDR_AXI_tb_opt
  vsim -lib work DDR_AXI_tb_opt
  set NumericStdNoWarnings 1
  set StdArithNoWarnings 1
  do {DDR_AXI_tb_wave.do}
  view wave
  view structure
  view signals

}


alias rerun {
   elab_ddr3
   log -rec /*
   run -all
}

源文件filelist.f

../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_ctrl_addr_decode.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_ctrl_read.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_ctrl_reg.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_ctrl_reg_bank.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_ctrl_top.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_ctrl_write.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_ar_channel.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_cmd_arbiter.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_cmd_fsm.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_simple_fifo.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_axi_upsizer.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_a_upsizer.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_carry_and.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_carry_latch_and.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_carry_latch_or.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_carry_or.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_command_fifo.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_comparator.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_comparator_sel.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_comparator_sel_static.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_r_upsizer.v
../../../src/axi_ddr/rtl/axi/mig_7series_v4_2_ddr_w_upsizer.v
../../../src/axi_ddr/rtl/clocking/mig_7series_v4_2_clk_ibuf.v
../../../src/axi_ddr/rtl/clocking/mig_7series_v4_2_infrastructure.v
../../../src/axi_ddr/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v
../../../src/axi_ddr/rtl/clocking/mig_7series_v4_2_tempmon.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_arb_mux.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_arb_row_col.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_arb_select.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_bank_cntrl.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_bank_common.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_bank_compare.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_bank_mach.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_bank_queue.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_bank_state.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_col_mach.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_mc.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_rank_cntrl.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_rank_common.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_rank_mach.v
../../../src/axi_ddr/rtl/controller/mig_7series_v4_2_round_robin_arb.v
../../../src/axi_ddr/rtl/ecc/mig_7series_v4_2_ecc_buf.v
../../../src/axi_ddr/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v
../../../src/axi_ddr/rtl/ecc/mig_7series_v4_2_ecc_gen.v
../../../src/axi_ddr/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v
../../../src/axi_ddr/rtl/ecc/mig_7series_v4_2_fi_xor.v
../../../src/axi_ddr/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v
../../../src/axi_ddr/rtl/ip_top/mig_7series_v4_2_mem_intfc.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_calib_top.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_init.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_top.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_poc_cc.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_poc_edge_store.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_poc_meta.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_poc_pd.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_poc_tap_base.v
../../../src/axi_ddr/rtl/phy/mig_7series_v4_2_poc_top.v
../../../src/axi_ddr/rtl/ui/mig_7series_v4_2_ui_cmd.v
../../../src/axi_ddr/rtl/ui/mig_7series_v4_2_ui_rd_data.v
../../../src/axi_ddr/rtl/ui/mig_7series_v4_2_ui_top.v
../../../src/axi_ddr/rtl/ui/mig_7series_v4_2_ui_wr_data.v
../../../src/axi_ddr/rtl/ddr3_mig_sim.v
../../../src/axi_ddr/rtl/ddr3.v

打开questasim执行仿真脚本，结果与vivado联合questasim仿真结果一致

3.1在transcript命令行中cd到脚本文件路径下

3.2 source脚本文件，并执行build编译源文件

3.3 rerun,启动波形仿真

波形界面

4.注意事项

4.1 MEM_BITS

*如果需要仿真的地址空间太大需要修改ddr3_parameters.vh文件中的MEM_BITS，否则会报ERROR： Memory overflow. Write to Address 7000fe with data xxx will be lost You must increase the MEM_BITS parameter of define MAX_MEM.

MEM_BITS定义了ddr3_model.sv中地址位宽，默认为15
在ddr3_parameters.vh文件中, 根据需要扩充MEM_BITS参数，比如修改至20。