16x16点阵滚动显示汉字可调整速度Verilog代码Quartus仿真

名称：16x16点阵滚动显示汉字可调整速度Verilog代码Quartus仿真（文末获取）

软件：Quartus

语言：Verilog

代码功能：

16x16点阵滚动显示汉字可调整速度

要求：控制16x16点阵显示器显示汉字，并滚动显示,可以调整滚动速度

1. 工程文件

2. 程序文件

3. 程序编译

4. testbench

5. 仿真图

附字模软件

部分代码展示:

module led_16X16(
input clk,//时钟
input speed_key,//调整滚动速度
output reg [15:0] hang,//行
output reg [15:0] lie//列
);
//汉字1--电
reg [15:0] word1_1=16'h0200;
reg [15:0] word1_2=16'h0200;
reg [15:0] word1_3=16'h0210;
reg [15:0] word1_4=16'h7FF8;
reg [15:0] word1_5=16'h4210;
reg [15:0] word1_6=16'h4210;
reg [15:0] word1_7=16'h7FF0;
reg [15:0] word1_8=16'h4210;
reg [15:0] word1_9=16'h4210;
reg [15:0] word1_10=16'h7FF0;
reg [15:0] word1_11=16'h4210;
reg [15:0] word1_12=16'h0200;
reg [15:0] word1_13=16'h0204;
reg [15:0] word1_14=16'h0204;
reg [15:0] word1_15=16'h01FC;
reg [15:0] word1_16=16'h0000;
//汉字2--子
reg [15:0] word2_1=16'h0000;
reg [15:0] word2_2=16'h3FF0;
reg [15:0] word2_3=16'h0010;
reg [15:0] word2_4=16'h0020;
reg [15:0] word2_5=16'h0040;
reg [15:0] word2_6=16'h0180;
reg [15:0] word2_7=16'h0104;
reg [15:0] word2_8=16'hFFFE;
reg [15:0] word2_9=16'h0100;
reg [15:0] word2_10=16'h0100;
reg [15:0] word2_11=16'h0100;
reg [15:0] word2_12=16'h0100;
reg [15:0] word2_13=16'h0100;
reg [15:0] word2_14=16'h0100;
reg [15:0] word2_15=16'h0500;
reg [15:0] word2_16=16'h0200;
reg [15:0] word [0:31];
//字符初始化
always@(posedge clk)
begin
word[0]<=word1_1;
word[1]<=word1_2;
word[2]<=word1_3;
word[3]<=word1_4;
word[4]<=word1_5;
word[5]<=word1_6;
word[6]<=word1_7;
word[7]<=word1_8;
word[8]<=word1_9;
word[9]<=word1_10;
word[10]<=word1_11;
word[11]<=word1_12;
word[12]<=word1_13;
word[13]<=word1_14;
word[14]<=word1_15;
word[15]<=word1_16;
word[16]<=word2_1;
word[17]<=word2_2;
word[18]<=word2_3;
word[19]<=word2_4;
word[20]<=word2_5;
word[21]<=word2_6;
word[22]<=word2_7;
word[23]<=word2_8;
word[24]<=word2_9;
word[25]<=word2_10;
word[26]<=word2_11;
word[27]<=word2_12;
word[28]<=word2_13;
word[29]<=word2_14;
word[30]<=word2_15;
word[31]<=word2_16;
end
reg [7:0]speed_step=8'd15;//调整步进(0~15)，越大滚动速度越快
reg speed_key_buf1=0;
reg speed_key_buf2=0;
wire speed_key_en;//按键上升沿
always @(posedge clk)
begin
speed_key_buf1<=speed_key;
speed_key_buf2<=speed_key_buf1;
end
assign speed_key_en=speed_key_buf1 & speed_key_buf2;
always @(posedge clk)
if(speed_key_en)
speed_step<=speed_step+8'd16;//按一次增加一次，speed_step越大，速度越慢
//对clk进行分频
reg clk_1=0;
reg [7:0] x=0;
integer n=0;
always @(posedge clk)
begin 
   if(x==speed_step)//speed_step越大，分频越大，clk_1越小
   begin 
       x<=0;
    clk_1=~clk_1;    
   end
   else
       x<=x+8'd1;
end
//列计数
reg [3:0] lie_cnt=4'd0;
always@(posedge clk)
lie_cnt<=lie_cnt+4'd1;

源代码

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