uart_driver:
vif和uart_config,build_phase get
uart_driver和monitor使用是根据波特率产生的时钟,故task gen_sample_rate:
virtual task gen_sample_rate();while(1)begin
@(posedge vif.clock);if(!vif.rst_n)begin
count=0;
sample_clk=0;
end
else begin
if(count==cfg.radio)begin
count=0;
sample_clk=1;
vif.baud_clk=1;
end
else begin
sample_clk=0;
vif.baud_clk=0;
count++;
end
end
end
endtask
task send(input uart_frame frame);
@(posedge sample_clk);
vif.txd=frame.start_bit;
……
@(posedge sample_clk);
vif.txd=1;repeat(frame.transmit_delay)begin
@(posedge sample_clk);
end
endtask
task tx_driver();
forever begin
seq_item_port.get_next_item(req);send(req);
seq_item_port.item_done();
end
endtask
task uart_driver::run_phase(uvm_phase phase);
forever begin
tx_driver();gen_sample_rate();
end
endtask