SRAM6264(8K*8)

• 引脚图
  
• 简化版，引脚逻辑图（抄PPT的
  

引脚功能：

• $A_{12}-A_0$，13根地址线，选择芯片内 $2^{13}$ 个存储单元中的任一个单元。
• $I/O_7-I/O_0$， 8根双向数据线，并行传送8位读/写数据
• $\overline{WE}$ 写入允许信号，低电平有效。
• $\overline{OE}$ 读出允许信号，低电半有效。
• $\overline{C{E}_1},C{E}_2$ 片选信号，两者均为低电平时才能对芯片进有读/写操作。
  
• Functional Description
  The CY6264 is a high-performance CMOS static RAM orga-nized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers. Both devices have an automatic power-down feature (CE1), reducing the power consumption by over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC.An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE in-puts are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins.The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity.