SpinalHDL AXI相关bus简单转换示例

1.下载SpinalHDL templet工程

2.配置build.sbt

ThisBuild / version := "1.0"
ThisBuild / scalaVersion := "2.11.12"
ThisBuild / organization := "org.example"

val spinalVersion = "1.9.1"
val spinalCore = "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion
val spinalLib = "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion
val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion)

lazy val projectname = (project in file("."))
  .settings(
    Compile / scalaSource := baseDirectory.value / "hw" / "spinal",
    libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin)
  )

fork := true

3.配置Config

package projectname

import spinal.core._
import spinal.core.sim._

object Config {
  def spinal = SpinalConfig(
    targetDirectory = "hw/gen",
    defaultConfigForClockDomains = ClockDomainConfig(
      resetActiveLevel = HIGH
    ),
    onlyStdLogicVectorAtTopLevelIo = true
  )

  def sim = SimConfig.withConfig(spinal).withFstWave
}

4.bus转换示例

package projectname

import spinal.core._
import spinal.lib._
import spinal.lib.bus.amba4.axi._
import spinal.lib.bus.amba4.axilite._
import spinal.lib.bus.amba4.axilite.AxiLite4Utils.Axi4Rich
import spinal.lib.bus.misc.SizeMapping
import javax.swing.text.FlowView

// -------------------------------------------

case class Axi42AxiLite4() extends Component {

  val config = Axi4Config(
    addressWidth = 48,
    dataWidth    = 512,
    idWidth      = 4
  )

  val io = new Bundle {
    val axi = slave(Axi4(config))
    val axilite = master(AxiLite4(AxiLite4Config(addressWidth = config.addressWidth, dataWidth = config.dataWidth)))
  }

  io.axi.toLite() >> io.axilite

}

// -------------------------------------------

case class TwoAxi42AxiLite4() extends Component {

  val masterConfig = Axi4Config(
    addressWidth = 48,
    dataWidth    = 512,
    idWidth      = 4,
    useRegion    = false,
    useQos       = false
  )
  val slaveConfig = masterConfig.copy(idWidth = 5)

  val io = new Bundle {
    val axi = Vec(slave(Axi4(masterConfig)), size = 2)
    val axilite = master(AxiLite4(AxiLite4Config(addressWidth = masterConfig.addressWidth, dataWidth = masterConfig.dataWidth)))
    axi.foreach(Axi4SpecRenamer(_))
  }

  noIoPrefix()

  val tmp_axi = Axi4(slaveConfig)

  val axiCrossBar = Axi4CrossbarFactory()
  axiCrossBar.addSlaves((tmp_axi, SizeMapping(0, 256 TiB)))
  io.axi.foreach(axiCrossBar.addConnection(_, Vec(tmp_axi, 1)))
  axiCrossBar.addPipelining(tmp_axi)(
    (masterPort, slavePort) => {
      masterPort.ar >-> slavePort.ar
      slavePort.r >-> masterPort.r
    }
  ) (
    (masterPort, slavePort) => {
      masterPort.aw >-> slavePort.aw
      masterPort.w >-> slavePort.w
      slavePort.b >-> masterPort.b
    }
  )
  axiCrossBar.build()

  tmp_axi.toLite() >> io.axilite

}

// -------------------------------------------

case class FourAxi42OneAxi() extends Component {

  val inConfig = Axi4Config(
    addressWidth = 32,
    dataWidth    = 512,
    idWidth      = 8,
    useRegion    = false,
    useQos       = false
  )
  val outConfig = inConfig.copy(idWidth = inConfig.idWidth + 2)

  val io = new Bundle {
    val axiIn = Vec(slave(Axi4(inConfig)), size = 4)
    val axiOut = master(Axi4(outConfig))
    axiIn.foreach(Axi4SpecRenamer(_))
    Axi4SpecRenamer(axiOut)
  }

  noIoPrefix()

  val axiCrossBar = Axi4CrossbarFactory()
  axiCrossBar.addSlaves((io.axiOut, SizeMapping(0, 4 GiB)))
  io.axiIn.foreach(axiCrossBar.addConnection(_, Vec(io.axiOut, 1)))
  axiCrossBar.addPipelining(io.axiOut)(
    (masterPort, slavePort) => {
      masterPort.ar >-> slavePort.ar
      slavePort.r >-> masterPort.r
    }
  ) (
    (masterPort, slavePort) => {
      masterPort.aw >-> slavePort.aw
      masterPort.w >-> slavePort.w
      slavePort.b >-> masterPort.b
    }
  )
  axiCrossBar.build()

}

// -------------------------------------------

case class FourAxiLite42OneAxiLite4() extends Component {

  val Config = AxiLite4Config(
    addressWidth = 32,
    dataWidth    = 32
  )

  val io = new Bundle {
    val inAxilite4 = Vec(slave(AxiLite4(Config)), size = 4)
    val localWrite = master(Stream(Bits(Config.addressWidth+Config.dataWidth bits)))
    val localReadCmd = master(Stream(Bits(Config.addressWidth bits)))
    val localReadAck = slave(Stream(Bits(Config.dataWidth bits)))
    inAxilite4.foreach(AxiLite4SpecRenamer(_))
  }

  noIoPrefix()

}

// -------------------------------------------

object xxm extends App {

  Config.spinal.generateSystemVerilog(FourAxi42OneAxi())
}

5.位宽转换示例

package projectname

import spinal.core._
import spinal.lib._
import spinal.lib.bus.amba4.axi._
import spinal.lib.bus.amba4.axi.Axi4Downsizer
import spinal.lib.bus.amba4.axilite._
import spinal.lib.bus.amba4.axilite.AxiLite4Utils.Axi4Rich
import spinal.lib.bus.misc.SizeMapping
import javax.swing.text.FlowView

// -------------------------------------------

case class spiHDL_AxiDownsizer() extends Component {

  val inConfig = Axi4Config(
    addressWidth = 33,
    dataWidth    = 512,
    idWidth      = 6
  )
  val outConfig = inConfig.copy(dataWidth = inConfig.dataWidth / 2)

  val io = new Bundle {
    val axiIn = slave(Axi4(inConfig))
    val axiOut = master(Axi4(outConfig))
    Axi4SpecRenamer(axiIn)
    Axi4SpecRenamer(axiOut)
  }

  noIoPrefix()

  val axi4_downsizer_inst = Axi4Downsizer(inConfig, outConfig)
  io.axiIn >> axi4_downsizer_inst.io.input
  axi4_downsizer_inst.io.output >> io.axiOut

}

// -------------------------------------------

object MyAxiDownsizer extends App {

  Config.spinal.generateSystemVerilog(spiHDL_AxiDownsizer())
}