1.在RTL code处赋待分析信号属性(* mark_debug ="true" *);
2.添加ILA相关脚本之前,需要synth相关的步骤:
launch_runs synth_1
wait_on_run synth_1
open_run synth_1
3.添加ILA相关脚本:
proc add_dbg_port {ila_inst_name probetype portsize portname} {
set probe [create_debug_port $ila_inst_name probe]
set_property port_width $portsize [get_debug_ports $probe]
set_property PROBE_TYPE $probetype [get_debug_ports $probe]
if ($portsize>1) {
set portexpr "${portname}[*]"
} else {
set portexpr "${portname}"
}
connect_debug_port $probe [lsort -dictionary [get_nets $portexpr]]
}
if {$debug_ila>0} {
create_debug_core ila_inst_name ila
set_property C_DATA_DEPTH 1024 [get_debug_cores ila_inst_name]
set_property C_TRIGIN_EN false [get_debug_cores ila_inst_name]
set_property C_TRIGOUT_EN false [get_debug_cores ila_inst_name]
set_property C_ADV_TRIGGER true [get_debug_cores ila_inst_name]
set_property C_INPUT_PIPE_STAGES 1 [get_debug_cores ila_inst_name]
set_property C_EN_STRG_QUAL true [get_debug_cores ila_inst_name]
set_property ALL_PROBE_SAME_MU true [get_debug_cores ila_inst_name]
# ALL_PROBE_SAME_MU_CNT must be:
# 1 if C_ADV_TRIGGER=false & C_EN_STRG_QUAL=false, 2 if C_ADV_TRIGGER=false & C_EN_STRG_QUAL=true, 4 otherwise
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores ila_inst_name]
set_property port_width 1 [get_debug_ports ila_inst_name/clk]
connect_debug_port ila_inst_name/clk [get_nets pl_pclk]
set_property port_width 5 [get_debug_ports ila_inst_name/probe0]
connect_debug_port ila_inst_name/probe0 [get_nets pl_ltssm*]
add_dbg_port ila_inst_name DATA_AND_TRIGGER 2 pl_equ_phase
}
4.添加ILA相关脚本之后,生成log,探针文件,以及执行opt_design:
if {$debug_ila>0} {
report_debug_core > debug_core.log
}
opt_design -directive Explore > opt_design.log
if {$debug_ila>0} {
write_debug_probes debug_nets.ltx
}
5.在工程脚本最前面添加一个ILA使能开关:
set debug_ila 1