Verilog新手上路学生实验

MUX41

verilog代码：

// module  top, 选择器（mux）的代码，
module top(
  IN0       ,   // input 1
  IN1       ,   // input 2
  IN2       ,   // input 3
  IN3       ,   // input 4
  S0        ,   // select
  S1        , 
  OUT       );  // out data

input IN0,IN1,IN2,IN3;// 选择器的四个输入数据信号
input S0,S1;              
output OUT;     // 选择器的输出数据信号
reg    OUT;
// 生成组合逻辑的代码
always @ (IN0 or IN1 or IN2 or IN3 or S0 or S1) begin
case({S1,S0})

 2'b00:OUT<=IN0;

 2'b01:OUT<=IN1;

 2'b10:OUT<=IN2;

 2'b11:OUT<=IN3;

default: OUT<=IN0;
endcase
end
endmodule
// endmodule top

RTL视图：

Flow Summary

4x4 crossbar switch circuit

verilog代码：

// module  top, a 4x4 crossbar switch circuit
module top(
  IN0       ,   // input 1
  IN1       ,   // input 2
  IN2       ,   // input 3
  IN3       ,   // input 4
  SEL0      ,   // select the output0 source 
  SEL1      ,   // select the output1 source 
  SEL2      ,   // select the output2 source 
  SEL3      ,   // select the output3 source 
  OUT0      ,   // output data 0
  OUT1      ,   // output data 1
  OUT2      ,   // output data 2
  OUT3      );  // output data 3

parameter WL = 16;
input [WL-1:0] IN0,IN1,IN2,IN3;
input SEL0,SEL1,SEL2,SEL3;
output[WL-1:0] OUT0,OUT1,OUT2,OUT3;

reg   [WL-1:0] OUT0,OUT1,OUT2,OUT3;
// get the OUT0
always @ (IN0 or IN1 or IN2 or IN3 or SEL0 or SEL1) begin
  if((SEL0)&&(SEL1))
    OUT0 = IN3;
  else if((!SEL0)&&(SEL1))
    OUT0 = IN2;
  else if((SEL0)&&(!SEL1))
	 OUT0 = IN1;
  else 
	 OUT0 = IN0;
end
// get the OUT1
always @ (IN0 or IN1 or IN2 or IN3 or SEL1 or SEL2) begin
  if((SEL1)&&(SEL2))
    OUT1 = IN3;
  else if((!SEL1)&&(SEL2))
    OUT1 = IN2;
  else if((SEL1)&&(!SEL2))
	 OUT1 = IN1;
  else
	 OUT1 = IN0;
end
// get the OUT2
always @ (IN0 or IN1 or IN2 or IN3 or SEL2 or SEL3) begin
  if((SEL2)&&(SEL3))
    OUT2 = IN3;
  else if((!SEL2)&&(SEL3))
    OUT2 = IN2;
  else if((SEL2)&&(!SEL3))
	 OUT2 = IN1;
  else 
	 OUT2 = IN0;
end
// get the OUT3
always @ (IN0 or IN1 or IN2 or IN3 or SEL3 or SEL0) begin
  if((SEL3)&&(SEL0))
    OUT3 = IN3;
  else if((!SEL3)&&(SEL0))
    OUT3 = IN2;
  else if((SEL3)&&(!SEL0))
	 OUT3 = IN1;
  else 
	 OUT3 = IN0;
end
endmodule
// endmodule top

RTL 视图：

Flow Summary