题目:
always@(posedge clk)
begin
a=0;
a<=1;
$display("%0b",a);
end
问题:输出多少;
答案是0;
解题:
分析1:
`timescale 1ns / 1ps
module ttt;
reg clk=0;
reg a=0;
reg b=1;
always@(posedge clk)
begin
a
题目:
always@(posedge clk)
begin
a=0;
a<=1;
$display("%0b",a);
end
问题:输出多少;
答案是0;
解题:
分析1:
`timescale 1ns / 1ps
module ttt;
reg clk=0;
reg a=0;
reg b=1;
always@(posedge clk)
begin
a