USRP B210固件、镜像下载及安装

一、下載固件和鏡像

1)使用UHD自帶工具下載

sudo uhd_images_downloader

2)從本網站下載,然後解壓到指定的路徑下。一般情況下,Linux系統需要解壓到以下路徑:

/esr/local/share/uhd/images

解壓後的文件大約是這樣的:

caton@caton-comp:~$ cd /usr/local/share/uhd/images
caton@caton-comp:/usr/local/share/uhd/images$ ls

003.010.001.000.tag                usrp_b200_fw.hex                       usrp_n210_fw.bin
bit                                                 usrp_b200mini_fpga.bin             usrp_n210_r2_fpga.bin
LICENSE                                    usrp_b205mini_fpga.bin             usrp_n210_r3_fpga.bin
octoclock_bootloader.hex       usrp_b210_fpga.bin                     usrp_n210_r4_fpga.bin
octoclock_r4_fw.hex                usrp_e100_fpga_v2.bin               usrp_n230_fpga.bit
usrp1_fpga_4rx.rbf                  usrp_e110_fpga.bin                      usrp_x300_fpga_HG.bit
usrp1_fpga.rbf                          usrp_e310_fpga.bit                       usrp_x300_fpga_HG.lvbitx
usrp1_fw.ihx                              usrp_e310_fpga_sg3.bit              usrp_x300_fpga_XG.bit
usrp2_fpga.bin                         usrp_e3xx_fpga_idle.bit               usrp_x300_fpga_XG.lvbitx
usrp2_fw.bin                             usrp_e3xx_fpga_idle_sg3.bit      usrp_x310_fpga_HG.bit
usrp_b100_fpga_2rx.bin       usrp_n200_fw.bin                           usrp_x310_fpga_HG.lvbitx
usrp_b100_fpga.bin               usrp_n200_r2_fpga.bin                 usrp_x310_fpga_XG.bit
usrp_b100_fw.ihx                   usrp_n200_r3_fpga.bin                 usrp_x310_fpga_XG.lvbitx
usrp_b200_fpga.bin              usrp_n200_r4_fpga.bin                 winusb_driver

2)下載固件和鏡像

uhd_usrp_probe

出現:

linux; GNU C++ version 5.4.0 20160609; Boost_105800; UHD_003.010.001.HEAD-0-g929e3b32

-- Loading firmware image: /usr/local/share/uhd/images/usrp_b200_fw.hex...
-- Detected Device: B210
-- Loading FPGA image: /usr/local/share/uhd/images/usrp_b210_fpga.bin... done
-- Operating over USB 3.
-- Detecting internal GPSDO.... No GPSDO found
-- Initialize CODEC control...
-- Initialize Radio control...
-- Performing register loopback test... pass
-- Performing register loopback test... pass
-- Performing CODEC loopback test... pass
-- Performing CODEC loopback test... pass
-- Setting master clock rate selection to 'automatic'.
-- Asking for clock rate 16.000000 MHz...
-- Actually got clock rate 16.000000 MHz.
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
  _____________________________________________________
 /
|       Device: B-Series Device
|     _____________________________________________________
|    /
|   |       Mboard: B210
|   |   revision: 4
|   |   product: 2
|   |   serial: 30AA045
|   |   name: 2000501894069
|   |   FW Version: 8.0
|   |   FPGA Version: 14.0
|   |   
|   |   Time sources:  none, internal, external, gpsdo
|   |   Clock sources: internal, external, gpsdo
|   |   Sensors: ref_locked
|   |     _____________________________________________________
|   |    /
|   |   |       RX DSP: 0
|   |   |   
|   |   |   Freq range: -8.000 to 8.000 MHz
|   |     _____________________________________________________
|   |    /
|   |   |       RX DSP: 1
|   |   |   
|   |   |   Freq range: -8.000 to 8.000 MHz
|   |     _____________________________________________________
|   |    /
|   |   |       RX Dboard: A
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Frontend: A
|   |   |   |   Name: FE-RX2
|   |   |   |   Antennas: TX/RX, RX2
|   |   |   |   Sensors: temp, rssi, lo_locked
|   |   |   |   Freq range: 50.000 to 6000.000 MHz
|   |   |   |   Gain range PGA: 0.0 to 76.0 step 1.0 dB
|   |   |   |   Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Frontend: B
|   |   |   |   Name: FE-RX1
|   |   |   |   Antennas: TX/RX, RX2
|   |   |   |   Sensors: temp, rssi, lo_locked
|   |   |   |   Freq range: 50.000 to 6000.000 MHz
|   |   |   |   Gain range PGA: 0.0 to 76.0 step 1.0 dB
|   |   |   |   Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Codec: A
|   |   |   |   Name: B210 RX dual ADC
|   |   |   |   Gain Elements: None
|   |     _____________________________________________________
|   |    /
|   |   |       TX DSP: 0
|   |   |   
|   |   |   Freq range: -8.000 to 8.000 MHz
|   |     _____________________________________________________
|   |    /
|   |   |       TX DSP: 1
|   |   |   
|   |   |   Freq range: -8.000 to 8.000 MHz
|   |     _____________________________________________________
|   |    /
|   |   |       TX Dboard: A
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Frontend: A
|   |   |   |   Name: FE-TX2
|   |   |   |   Antennas: TX/RX
|   |   |   |   Sensors: temp, lo_locked
|   |   |   |   Freq range: 50.000 to 6000.000 MHz
|   |   |   |   Gain range PGA: 0.0 to 89.8 step 0.2 dB
|   |   |   |   Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Frontend: B
|   |   |   |   Name: FE-TX1
|   |   |   |   Antennas: TX/RX
|   |   |   |   Sensors: temp, lo_locked
|   |   |   |   Freq range: 50.000 to 6000.000 MHz
|   |   |   |   Gain range PGA: 0.0 to 89.8 step 0.2 dB
|   |   |   |   Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Codec: A
|   |   |   |   Name: B210 TX dual DAC
|   |   |   |   Gain Elements: None







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