vivado中遇到的错误

（1）

报错：

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_IBUF] >

reset_IBUF_inst (IBUF.O) is locked to IOB_X1Y66
and reset_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances
 

问题段：

    reg point = 1'b1 ;
    smg U3(.clock(clock),.num(num),.point(point),.select(sw[3]),.cm(sw[2]),.CX(out_smgC));
    
        always @ ( reset )
            begin
                if( reset )
                    point = ~point;
                else
            end

这种问题是因为：

从外部来的（接到板子上的）always语句中的敏感信号为时钟以外的外部信号，因为Vivado在处理外部时钟信号的时候会自动添加BUFG模块来去除时钟的抖动，但是其他的信号就不会这样做，这样的话在always语句的敏感信号列表中使用没有去抖动的外部信号就有可能导致系统不稳定，所以会出现这个错误。

需要在IO配置文件最后添加：set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_IBUF] 

原文：https://blog.csdn.net/cnkuaike123/article/details/48403067