帮忙看看这段程序啊

帮忙看看这段程序啊 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity san is port(clk:in std_logic;      sanut std_logic_vector(7 downto 0)); end; architecture behave of san is signal up:std_logic; signal san1:std_logic_vector(7 downto 0); begin    process(clk,san1)      begin       if clk'event and clk='1' then         if up='1'  then  san1<=san1+1;            else san1<=san1-1;          end if;       end if;       san<=san1;      end process;    process(san1)      begin        if san1="00000000" then up<='1';             else if san1="11111111" then up<='0';           else null;             end if;        end if;   end process; end behave; 要设计的是一个自行可逆计数器，即计到最大值１１１１１１１１时，开始往下计数，当减计数器，减到零时又做加计数器．可是运行是有警告， Warning: VHDL Process Statement warning at san.vhd(21): signal or variable "up" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "up" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design. Warning: Timing Analysis found one or more latches implemented as combinational loops         Warning: Node "up" is a latch Warning: Timing Analysis found one or more latches implemented as combinational loops         Warning: Node "up" is a latch 仿真时只能计到１１１１００００就开始减，但如果改为九位或六位就没有问题，请问是什么原因？