perl实现verilog ifdef所在域的判断

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功能描述

perl实现verilog ifdef所在域的判断。
1. emacs verilog-mode用于实例化很方便;但是常见项目,均存在大量ifdef的预编译命令。而emacs verilog-mode不支持ifdef。
2. 手动实例化,往往带来不可预料的错误。

功能演示

这里写图片描述这里写图片描述

代码

#!/usr/bin/perl
use strict;
use warnings;

open my $ifile,"<",$ARGV[0] or die;
my $ifile_num=0;
my @tag;
my @state=("ifdef_DEFF","ifndef_DEFG");
while(<$ifile>){
    #print "========like verilog fsm state=========================\n";
    $ifile_num=$ifile_num+1;
    if($_ =~ /\s*\`ifdef\s+([0-9a-zA-Z_]+)/){
        push @tag,"ifdef_$1";
    }
    if($_ =~ /\s*\`ifndef\s+([0-9a-zA-Z_]+)/){
        push @tag,"ifndef_$1";
    }
    if($_ =~ /\s*\`else/){
        my $current_tag = pop @tag;
        if($current_tag =~ /ifndef_([0-9a-zA-Z_]+)/){
            push @tag,"ifdef_$1";
        }
        if($current_tag =~ /ifdef_([0-9a-zA-Z_]+)/){
            push @tag,"ifndef_$1";
        }
    }
    if($_ =~ /\s*\`endif/){
        pop @tag;
    }
    #print "========debug information=========================\n";
    print "$ifile_num:\@tag=@tag";
    print "\n";
    #print "========action by debug information=========================\n";
    if(&compare(\@tag,\@state)){
        print "$_";
    }
}
close $ifile;

sub compare()
{
    my $flag=0;
    my ($first,$second)=@_;
    if (@$first==@$second) # the number of the array , don't use length()
    {
        for(my $i=0;$i<@$first;$i++)
        {
            #if($first->[$i]!=$second->[$i])
            if($first->[$i] ne $second->[$i])
            {
                $flag=1;
                #print "$first->[$i] ne $second->[$i]\n";
            }
        }
    }
    else
    {
        $flag=1;
    }
    if( $flag==1)
    {
        #print "two arrays are not equal\n";
        return 0;
    }
    else
    {
        #print "two arrays are  equal\n";
        return 1;
    }
}

代码小结

利用数组,作为状态

利用数组匹配,作为状态判断,并执行相应任务

数组匹配,子函数compare

iscas2spice spice netlist generation tool -- version 2.2 by Jingye Xu @ VLSI Group, Dept. of ECE, UIC, June, 2008 This tool reads the ISCAS85 benchmark circuit "*.bench" file and translate the file into SPICE netlist using the given technology and the standard cell library. platform: linux x86 sytem Input: ISCAS85 benchmark circuit: *.bench; standard cell library: stdcells.sclb; standard cell models: stdcells.lib; interconnect paramaters: *.int; Output: SPICE netlist: out.sp The whole procedure of the tools can be divided into several steps: 1. Gate replacement: replace the gates that can't be found in the with the gates in the standard cell lib. (break.pl) Output: *.bench, *.bench.bak 2. Generate the GSRC files: generate the GSRC files for the fengshui placer. (gsrcgen.pl) Output: gsrcfile/iscas.* 3. Placement: using the fengshui placement tool to perform the component placement. (fs50) Output: gsrcfile/iscas_fs50.pl 4. Generate ISPD file: tanslate the placement results into ISPD98 format file that can be used as the input of the global router. (gsrc2ispd.pl) Output: gsrcfile/iscas.laby.txt 5. Perform the routing: use the labyrinth global router to perform the routing. (mazeRoute) Output: gsrcfile/output 6. Generate the SPICE netlist: use all the available information to generate the final SPICE netlist. (spicegen.pl) Output: out.sp Usage: iscas2spice.pl Iscas85BenchmarkFile [-C/L/N] options: -C :default value, use the RC model for interconnect -L :use the RLC model for interconnect -N :treat interconnect as short circuit wire This package used the fengshui placement tools and labyrinth global routing tools, for information regarding these two free tools, please vist: http://www.ece.ucsb.edu/~kastner/labyrinth/ http://vlsicad.cs.binghamton.edu/software.html For information regarding this software itself please visit: http://wave.ece.uic.edu/~iscas2spice Many thanks to my advisor Masud H. Chowdhury for his support!
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