Verilog `ifdef 条件编译

Verilog支持编译器指令，可以通过编译器指令选择部分代码是否被使用。

语法格式

关键字主要有以下几种：ifdef、ifndef、else、elsif、endif和define

主要以下几种格式：

//style #1:Only singleifdef
`ifdef <FLAG>
    //statements
`endif

// style #2:ifdef withelse part
`ifdef <FLAG>
    //Statements
`else
    //statements
`endif

// style #3:ifdef with additional ifdefs
`ifdef<FLAG1>
    //statements
`elsif <FLAG2>
    //statements
`elsif <FLAG3>
    //statements
`else
    //statements
`endif

示例#1：ifdef

module my_design (
	input clk, d,
	
	`ifdef INCLUDE_RSTN
	input rstn,
	`endif
	
	output reg q
);

always @ (posedge clk)
begin
`ifdef INCLUDE_RSTN
    if (!rstn)
    begin
        q <= 0;
    end
    else
`endif
    begin
        q <= d;
    end
end

endmodule

仿真文件：

module tb;
reg clk, d, rstn;
wire q;
reg [3:0] delay;

my_design u0 ( .clk(clk), .d(d),
`ifdef INCLUDE_RSTN
               .rstn(rstn),
`endif
               .q(q));

always #10 clk = ~clk;

initial
begin
    integer i;

    {d, rstn, clk} <= 0;

    #20 rstn <= 1;
    for (i = 0 ; i < 20; i=i+1)
    begin
        delay = $random;
        #(delay) d <= $random;
    end

    #20 $finish;
end
endmodule

可以通过指定编译器指令：+define+INCLUDE RSTN，直接使用``define INCLUDE_RSTN`的方式来包含RSTN功能。

示例#2：ifdef和elsif

module tb;
initial
begin

`ifdef MACRO1
    $display ("This is MACRO1");

    `elsif MACRO2
           $display ("This is MACRO2");

`endif

end
endmodule

仿真结果：

# With no macros defined
ncsim> run
ncsim: *W,RNQUIE: Simulation is complete.

# With +define+MACRO1
ncsim> run
This is MACRO1
ncsim: *W,RNQUIE: Simulation is complete.

# With +define+MACRO2
ncsim> run
This is MACRO2
ncsim: *W,RNQUIE: Simulation is complete.

示例#3：ifndef和elsif

module tb;
initial
begin

    `ifndef MACRO1
            $display ("This is MACRO1");

    `elsif MACRO2
           $display ("This is MACRO2");

`endif

end
endmodule

仿真结果：

# With no macros defined ncsim>run This is MACRO1
ncsim:*W, RNQUIE: Simulation is complete.

# With +define+MACRO1
ncsim>run ncsim:*W, RNQUIE: Simulation is complete.

# With +define+MACR02
ncsim>run This is MACRO1
ncsim:*W, RNQUIE: Simulation is complete.

# With+define+MACRO1+define+MACRO2
ncsim>run This is MACR02
ncsim:*W, RNQUIE: Simulation is complete.

示例#4：ifdef的嵌套

  
module tb;
  initial begin
    `ifdef FLAG
    	$display ("FLAG is defined");
    	`ifdef NEST1_A
    		$display ("FLAG and NEST1_A are defined");
    		`ifdef NEST2
    			$display ("FLAG, NEST1_A and NEST2 are defined");
    		`endif
    	`elsif NEST1_B
    		$display ("FLAG and NEST1_B are defined");
    		`ifndef WHITE
    			$display ("FLAG and NEST1_B are defined, but WHITE is not");
    		`else
    			$display ("FLAG, NEST1_B and WHITE are defined");
    		`endif
    	`else
    		$display ("Only FLAG is defined");
    	`endif
    `else
    	$display ("FLAG is not defined");
    `endif
  end
endmodule

仿真结果：

# Without defining any macro
ncsim> run
FLAG is not defined
ncsim: *W,RNQUIE: Simulation is complete.

# With +define+FLAG +define+NEST1_B
ncsim> run
FLAG is defined
FLAG and NEST1_B are defined
FLAG and NEST1_B are defined, but WHITE is not
ncsim: *W,RNQUIE: Simulation is complete.

# With +define+FLAG +define+NEST1_B +define+WHITE
ncsim> run
FLAG is defined
FLAG and NEST1_B are defined
FLAG, NEST1_B and WHITE are defined
ncsim: *W,RNQUIE: Simulation is complete.

# With +define+FLAG
ncsim> run
FLAG is defined
Only FLAG is defined
ncsim: *W,RNQUIE: Simulation is complete.

# With +define+WHITE
ncsim> run
FLAG is not defined
ncsim: *W,RNQUIE: Simulation is complete.

# With +define+NEST1_A
ncsim> run
FLAG is not defined
ncsim: *W,RNQUIE: Simulation is complete.

FROM：verilog-ifdef-conditional-compilation