-
A Bit of Practice
Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits:
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );//
// assign { ... } = { ... };
assign {w,x,y,z} = {a,b,c,d,e,f,2'b11};
endmodule
-
Vectorr
module top_module(
input [7:0] in,
output [7:0] out
);
// assign out[7:0] = in[0:7]; 错误示例
//assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]}; //第一种方法
generate
genvar i;
for(i = 0; i <= 7;i = i + 1)
begin:conv
assign out[i] = in[7-i];
end
endgenerate
endmodule
-
Vector4
module top_module (
input [7:0] in,
output [31:0] out );//
// assign out = { replicate-sign-bit , the-input };
assign out[31:0] = {{24{in[7]}},in[7:0]};
endmodule
-
Vector5
XNOR-异或
module top_module (
input a, b, c, d, e,
output [24:0] out );//
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
assign out = ~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}} ^ {5{a,b,c,d,e}};
endmodule
-
Module
module top_module ( input a, input b, output out );
//mod_a u_mod_a(a,b,out);
mod_a u_mod_a(
.in1(a),
.in2(b),
.out(out)
);
endmodule