FPGA错误[Place 30-574] 以及串口乱码错误

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sys_clk_IBUF] >

    sys_clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y102
     and BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

 

使用串口时遇到此错误，网上查找之后发现添加该语句可以消除错误但是串口还是乱码。

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sys_clk]

此时由于我直接把FPGA的时钟线来作为串口的时钟线所导致的。

添加BUFG即可。

 

 在顶层模块中例化。