Verilog实验-交通灯

功能模块

module traffic(clk,rst);
input clk,rst;
reg[3:0] ns,cs;
reg red,yellow,green;
parameter on=1'b1,off=1'b0;
parameter s0=4'd0,s1=4'd1,s2=4'd2;
reg[3:0] counter;
always@(posedge clk or negedge rst)
begin 
  if(rst)
    begin
    counter