FPGA 差分信号 激励写法

200MHz差分信号，激励写法。

module tb_test(
    );
 reg clk_i;
 reg sys_rst;
 
 
 wire clk_out1;
 
 test1 uut(
    .sys_clk_p (clk_i),
    .sys_clk_n (~clk_i),
    .sys_rst   (sys_rst),
    
    .clk_out1  (clk_out1)
 );
 
 
 initial begin
    clk_i = 0;
    sys_rst = 0;
    
    #1000;
    sys_rst = 1;
    #100;
    

end

always #(2.5) clk_i = ~clk_i;

endmodule