1、时钟信号的产生
两种方法:并行赋值语句,进程。
并行赋值语句
--产生对称信号
clk <= NOT clk AFTER 20 NS;--20ns之后为 not clk
--产生不对称信号
w_clk <= '0' AFTER period/4 WHEN w_clk = '1' ELSE --'0' AFTER period/4表示:period/4之后为0
'1' AFTER 3*period/4 WHEN w_clk = '0'ELSE
进程
--产生对称信号
clk_gen1 : PROCESS
CONSTANT period : TIME := 20 NS;
BEGIN
clk <= '1';
WAIT FOR period/2;
clk <= '0';
WAIT FOR period/2;
END PROCESS;
--产生不对称信号
clk _gen2 : PROCESS
CONSTANT period : TIME := 20 NS;
BEGIN
clk <= '1';
WAIT FOR period/4;
clk <= '0';
WAIT FOR 3*period/4;
END PROCESS;
2、复位信号
reset <= '0','1'AFTER 20 NS,'0' AFTER 40 NS;
reset <= '0', '1'AFTER 100 NS, '0'AFTER 180 NS,'1'AFTER 210 NS;
3、周期性信号
--周期性信号
SIGNAL CLK1,CLK2 : STD_LOGIC := 0;
PROCESS
BEGIN
CLK1 <= '1' AFTER 5 NS,'0' AFTER 10 NS,'1' AFTER 20 NS, '0' AFTER 25 NS;
CLK2 <= '1' AFTER 10 NS,'0' AFTER 20 NS, '1'AFTER 25 NS, '0' AFTER 30 NS;
WAIT FOR 35 NS;
END PROCESS;