Exams/m2014 q6b

Consider the state machine shown below, which has one input w and one output z.

Assume that you wish to implement the FSM using three flip-flops and state codes y[3:1] = 000, 001, ... , 101 for states A, B, ... , F, respectively. Show a state-assigned table for this FSM. Derive a next-state expression for the flip-flop y[2].

Implement just the next-state logic for y[2]. (This is much more a FSM question than a Verilog coding question. Oh well.)

module top_module (
    input [3:1] y,
    input w,
    output Y2);

    parameter [3:1]a=3'd0;
    parameter [3:1]b=3'd1;
    parameter [3:1]c=3'd2;
    parameter [3:1]d=3'd3;
    parameter [3:1]e=3'd4;
    parameter [3:1]f=3'd5;
    
    reg [3:1]next_state;
    
    /*always@(posedge clk)begin
        if(reset)
            state<=a;
        else
            state<=next_state;
    end*/
    
    always@(*)begin
        case(y)
            a:next_state<=w?a:b;
            b:next_state<=w?d:c;
            c:next_state<=w?d:e;
            d:next_state<=w?a:f;
            e:next_state<=w?d:e;
            f:next_state<=w?d:c;
        default:next_state<=a;
        endcase
    end
  /*  always@(*)begin
        case(y[3:1])
            000:Y2<=a[2];
            001:Y2<=b[2];
            010:Y2<=c[2];
            011:Y2<=d[2];
            100:Y2<=e[2];
            101:Y2<=f[2];
            default:Y2<=a[2];
        endcase
    end*/
    assign Y2=next_state[2];            
endmodule

 //的部分为自己之前的思路.我所设置的模块在于理解题目:y[3:1]如果是000-101的时候,分别对应于a-f,所以输出Y[2],其实也就是分别输出y[2]的对应下一个阶段,但是后面思考一下,错误原因在于,输入和输出对应的阶段还是两个阶段,一个是当前阶段,一个是下一个阶段,所以如果是按照我注释的思路去进行,则应该主要观察w?之后的数据,根据其中的数据对Y2进行计算.当然了题目的意思在于Y2的真实结果其实就是next_state[2].所以不加reset和clk,直接采用组合电路,运用case语句去进行编程就相当简单了.