https://hdlbits.01xz.net/wiki/Exams/m2014_q6b
module top_module (
input [3:1] y,
input w,
output Y2);
reg [3:1]d;
parameter A=0,B=1,C=2,D=3,E=4,F=5;
always@(*)
begin
case(y)
A:d = w?A:B;
B:d = w?D:C;
C:d = w?D:E;
D:d = w?A:F;
E:d = w?D:E;
F:d = w?D:C;
endcase
end
assign Y2 = d[2];
endmodule