module D_trigger(
input clk ,
input rst_n ,//Asynchronous set to 0 (triggered by rising edge, active at high level)
input clr ,//Asynchronous set to 1 (triggered by rising edge, active at high level)
input D ,
output reg Q ,
output QN
);
always @(posedge clk or posedge rst_n or posedge clr) begin
if(rst_n)begin
Q <= 0 ;
end else begin
if(clr)begin
Q <= 1 ;
end else begin
Q <= D ;
end
end
end
assign QN = ~Q ;
endmodule