module complex_fsm (
input wire sys_clk ,
input wire sys_rst_n ,
input wire pi_money_one ,
input wire pi_money_half ,
output reg po_cola ,
output reg po_money
);
// define signal
wire [01:00] money ;
reg [04:00] state ;
// define parameter
parameter IDLE = 5'b00001 ,
HALF = 5'b00010 ,
ONE = 5'b00100 ,
ONE_HALF = 5'b01000 ,
TWO = 5'b10000 ;
// money
assign money = ( pi_money_half ) ? 2'b01 : ( pi_money_one ) ? 2'b10 : 2'b00 ;
// state
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
state <= IDLE ;
end else begin
case ( state )
IDLE : begin
if( money == 2'b01 ) begin
state <= HALF ;
end else begin
if( money == 2'b10 ) begin
state <= ONE ;
end else begin
state <= IDLE ;
end
end
end
HALF : begin
if( money == 2'b01 ) begin
state <= ONE ;
end else begin
if( money == 2'b10 ) begin
state <= ONE_HALF ;
end else begin
state <= HALF ;
end
end
end
ONE : begin
if( money == 2'b01 ) begin
state <= ONE_HALF ;
end else begin
if( money == 2'b10 ) begin
state <= TWO ;
end else begin
state <= ONE ;
end
end
end
ONE_HALF : begin
if( money == 2'b01 ) begin
state <= TWO ;
end else begin
if( money == 2'b10 ) begin
state <= IDLE ;
end else begin
state <= ONE_HALF ;
end
end
end
TWO : begin
if( money == 2'b01 || money == 2'b10 ) begin
state <= IDLE ;
end else begin
state <= TWO ;
end
end
default : state <= IDLE ;
endcase
end
end
// po_cola
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
po_cola <= 0 ;
end else begin
if( (state == ONE_HALF && money == 2'b10) || (state == TWO && money != 2'b00) ) begin
po_cola <= 1'b1 ;
end else begin
po_cola <= 0 ;
end
end
end
// po_money
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
po_money <= 0 ;
end else begin
if(state == TWO && money == 2'b10) begin
po_money <= 1 ;
end else begin
po_money <= 0 ;
end
end
end
endmodule