同步和异步清零:
敏感信号不同,同步:posedge clk ;异步:posedge clk or reset clk.
module top_module (
input clk,
input d,
input r, // synchronous reset
output q);
always @(posedge clk)
begin
if(r) q=0;
else q=d;
end
endmodule
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q);
always @(posedge clk or posedge ar) //异步清零
if(ar) q=0;
else q=d;
endmodule