Exams/ece241 2014 q5b_HDLbits

1、The following diagram is a Mealy machine implementation of the 2's complementer. Implement using one-hot encoding.

简单的merely型状态机设计，能画出上面的状态图就很简单了。

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    parameter  A=0,B=1;
    reg [1:0] state,next_state;
    always @(*)
        begin
            case(state)
                A:next_state<=(x)? B:A;
                B:next_state<=B;
            endcase 
        end
     
    always @(posedge clk,posedge areset )    
        begin
            if(areset) state<=A;
            else
                state<=next_state;
        end
    assign z = (state==A&&!x)? 0:(state==A&&x)? 1:(state==B&&x)?0:(state==B&&!x)?1:0;
    
endmodule