单AXI总线多通道仲裁状态机V2.0（代码+tb文件）

NoNoUnknow

已于 2024-03-14 11:38:01 修改

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分类专栏： DDR3 FPGA学习 AXI 文章标签： fpga开发

于 2024-03-11 18:08:35 首次发布

本文链接：https://blog.csdn.net/NoNoUnknow/article/details/136631242

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纯做记录；

暂不放完。

参考：【数字IC设计】循环优先级仲裁器的 verilog实现（原理、源码、仿真）_轮询仲裁器verilog代码-CSDN博客

V1.0：修好了有效在高位的问题，增加了状态机方便控制AXI接口地址等；

循环优先级仲裁~位屏蔽仲裁算法_循环优先级仲裁器-CSDN博客

module  Aribe_LoopPrior_State_v1 (
    input   wire            I_clk                       ,
    input   wire            I_Rst_n                     ,
    //Port
    //ch0
    input   wire            I_ch0_req                   ,
    input   wire            I_ch0_start                 ,
    input   wire            I_ch0_end                   ,
    output  wire            O_ch0_vaild                 ,
    //ch1
    input   wire            I_ch1_req                   ,
    input   wire            I_ch1_start                 ,
    input   wire            I_ch1_end                   ,
    output  wire            O_ch1_vaild                 ,
    //ch2
    input   wire            I_ch2_req                   ,
    input   wire            I_ch2_start                 ,
    input   wire            I_ch2_end                   ,
    output  wire            O_ch2_vaild                 ,
    //ch3
    input   wire            I_ch3_req                   ,
    input   wire            I_ch3_start                 ,
    input   wire            I_ch3_end                   ,
    output  wire            O_ch3_vaild                 ，
    //AXI Port
);

    //-----------------------------------------------------------------//
        localparam  state_idle  = 10'b0000_0000_01;
        localparam  state_aribe = 10'b0000_0000_10;

        localparam  state_ch0_0 = 10'b0000_0001_00;
        localparam  state_ch0_1 = 10'b0000_0010_00;

        localparam  state_ch1_0 = 10'b0000_0100_00;
        localparam  state_ch1_1 = 10'b0000_1000_00;

        localparam  state_ch2_0 = 10'b0001_0000_00;
        localparam  state_ch2_1 = 10'b0010_0000_00;

        localparam  state_ch3_0 = 10'b0100_0000_00;
        localparam  state_ch3_1 = 10'b1000_0000_00;

`timescale  1ns / 1ps

module tb_Aribe_LoopPrior_State_v1;

// Aribe_LoopPrior_State_v1 Parameters
parameter PERIOD  = 10;


// Aribe_LoopPrior_State_v1 Inputs
reg   I_clk                                ;
reg   I_Rst_n                              ;
reg   I_ch0_req                            ;
reg   I_ch0_start                          ;
reg   I_ch0_end                            ;
reg   I_ch1_req                            ;
reg   I_ch1_start                          ;
reg   I_ch1_end                            ;
reg   I_ch2_req                            ;
reg   I_ch2_start                          ;
reg   I_ch2_end                            ;
reg   I_ch3_req                            ;
reg   I_ch3_start                          ;
reg   I_ch3_end                            ;

// Aribe_LoopPrior_State_v1 Outputs
wire  O_ch0_vaild                          ;
wire  O_ch1_vaild                          ;
wire  O_ch2_vaild                          ;
wire  O_ch3_vaild                          ;

initial begin
    I_clk = 0;
end
always #(PERIOD/2) I_clk = ~ I_clk;

initial begin
    I_Rst_n <= 1'b0;
    repeat (100) @(posedge I_clk);
    I_Rst_n <= 1'b1;
end

initial begin  
    repeat (10) @(posedge I_clk);
    I_ch0_start <= 1'b0;
    I_ch0_end   <= 1'b0;
    I_ch1_start <= 1'b0;
    I_ch1_end   <= 1'b0;
    I_ch2_start <= 1'b0;
    I_ch2_end   <= 1'b0;
    I_ch3_start <= 1'b0;
    I_ch3_end   <= 1'b0;
    {I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req} <= 4'b0000;
    @(posedge I_Rst_n);
    {I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req} <= 4'b1011;
    repeat (1) @(posedge I_clk);
    {I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req} <= 4'b0000;
    @(posedge O_ch0_vaild);
    repeat (2) @(posedge I_clk);
    I_ch0_start <= 1'b1;
    repeat (1) @(posedge I_clk);
    I_ch0_start <= 1'b0;
    repeat (64) @(posedge I_clk);
    I_ch0_end <= 1'b1;
    repeat (1) @(posedge I_clk);
    I_ch0_end <= 1'b0;
    repeat (64) @(posedge I_clk); 
    {I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req} <= 4'b1001;
    repeat (1) @(posedge I_clk);
    {I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req} <= 4'b0000;
    @(posedge O_ch3_vaild);
    repeat (2) @(posedge I_clk);
    I_ch3_start <= 1'b1;
    repeat (1) @(posedge I_clk);
    I_ch3_start <= 1'b0;
    repeat (64) @(posedge I_clk);
    I_ch3_end <= 1'b1;
    repeat (1) @(posedge I_clk);
    I_ch3_end <= 1'b0;
    repeat (64) @(posedge I_clk); 
end

Aribe_LoopPrior_State_v1  u_Aribe_LoopPrior_State_v1 (
    .I_clk                   ( I_clk         ),
    .I_Rst_n                 ( I_Rst_n       ),
    .I_ch0_req               ( I_ch0_req     ),
    .I_ch0_start             ( I_ch0_start   ),
    .I_ch0_end               ( I_ch0_end     ),
    .I_ch1_req               ( I_ch1_req     ),
    .I_ch1_start             ( I_ch1_start   ),
    .I_ch1_end               ( I_ch1_end     ),
    .I_ch2_req               ( I_ch2_req     ),
    .I_ch2_start             ( I_ch2_start   ),
    .I_ch2_end               ( I_ch2_end     ),
    .I_ch3_req               ( I_ch3_req     ),
    .I_ch3_start             ( I_ch3_start   ),
    .I_ch3_end               ( I_ch3_end     ),

    .O_ch0_vaild             ( O_ch0_vaild   ),
    .O_ch1_vaild             ( O_ch1_vaild   ),
    .O_ch2_vaild             ( O_ch2_vaild   ),
    .O_ch3_vaild             ( O_ch3_vaild   )
);
endmodule