Circuits--Sequential--FSM-Q3b~Q3c

1. q3b

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
    
    parameter s0 = 3'b000;
    parameter s1 = 3'b001;
    parameter s2 = 3'b010;
    parameter s3 = 3'b011;
    parameter s4 = 3'b100;
    
    reg[2:0] state;
    reg[2:0] next_state;
    
    always@(*)
        begin
            case(state)
                s0:
                    begin
                    	if(x) next_state = s1;
                		else  next_state = s0;
                    end
                s1:
                    begin
                        if(x) next_state = s4;
                		else  next_state = s1;
                    end
                s2:
                    begin
                    	if(x) next_state = s1;
                		else  next_state = s2;
                    end
                s3:
                    begin
                        if(x) next_state = s2;
                		else  next_state = s1;
                    end
                s4:
                    begin
                        if(x) next_state = s4;
                		else  next_state = s3;
                    end
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset)
                state <= s0;
            else
                state <= next_state;
        end
    
    assign z = (state == s3 || state == s4);
    

endmodule

2. q3c

直接组合逻辑

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output z,
    output Y0
);
    
    assign z = ((y == 3'b011)||(y == 3'b100));
    assign Y0 = ((~y[2]&y[0])|(y==3'b100))&~x | (~y[2]&~y[0])&x;
  

endmodule