Quartus 软件设计中常见错误分析

1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement,
but is not in sensitivity list
----没把 singal 放到 process()中
2 Warning: Found pins ing as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
-=-----可能是说设计中产生的触发器没有使能端
3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan"
of mode out cannot be read. Change object mode to buffer or inout.
------信号类型设置不对,out 当作 buffer 来定义
4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"
-------引用的例化元件未定义实体--entity "clk_gen"
5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks
-- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clk_gen:clk_gen1/clk_incr" as buffer
Info: Detected ripple clock "clk_gen:clk_gen1/clk_scan" as buffer
6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout"
may not be assigned a new in every possible path through the Process Statement. Signal or
variable "dataout" holds its previous in every path with no new assignment, which may create
a combinational loop in the current design.
7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside
the Process Statement but isn''t in the Process Statement''s sensivitity list
-----缺少敏感信号
8 Warning: No clock transition on "counter_bcd7:counter_counter_clk/q_sig[3]" register
9 Warning: Reduced register "counter_bcd7:counter_counter_clk/q_sig[3]" with stuck clock
port to stuck GND
10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock
"class[1]" with clock skew larger than data delay. See Compilation Report for details.
11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock
"sign" with clock skew larger than data delay. See Compilation Report for details.
12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be
associated with formal port "class" of mode "out"
------两者不能连接起来
1 13 Warning: Ignored node in vector source file. Can''t find corresponding node name
"class_sig[2]" in design.
------没有编写 testbench 文件,或者没有编辑输入变量的值 testbench 里是元件申明和映射
14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design
entity does not have std_logic_vector type that is specified for the same generic in the
associated component
---在相关的元件里没有当前文件所定义的类型
15 Error: VHDL error at tongbu.vhd(16): can''t infer register for signal "gate" because
signal does not hold its outside clock edge
16 Warning: Found clock high time violation at 1000.0 ns on register
"/fcounter/lpm_counter:temp_rtl_0/dffs[4]"
17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector
source file node.
---"temp[19]"被优化掉了
18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND
19 Warning: Design contains 2 input pin(s) that do not drive logic
Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "sign"
------输出信号与输入信号无关,
20 Warning: Found clock high time violation at 16625.0 ns on register "/impulcomp/gate1"
21 Error: VHDL error at impulcomp.vhd(19): can''t implement clock enable condition specified
using binary operator "or"
22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned
to formal parameter "alarm", but formal parameter is not declared
-------连接表错误,形参"alarm"赋值给实参,形参没定义,可能是形参与实参的位置颠倒了,规定
形参在实参之前。
23 Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors
--------因为前一个错误而导致的错误
24 Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does not agree
with its usage as std_logic type
--------"alarm"的定义类型与使用的类型不一致
25 Error: VHDL error at shift_reg.vhd(24): can''t synthesize logic for statement with
conditions that test for the edges of multiple clocks
-------同一进程中含有两个或多个 if(edge)条件,(一个进程中之能有一个时钟沿)
2 26 Error: Can''t resolve multiple constant drivers for net "datain_reg[22]" at
shift_reg.vhd(19)
27 can''t infer register for signal "num[0]" because signal does not hold its outside clock
edge
28Error: Can''t elaborate top-level user hierarchy
29 Error: Can''t resolve multiple constant drivers for net "cs_in" at
led_key.vhd(32) ----------有两个以上赋值语句,不能确定“cs_in”的值,
30 Warning: Ignored node in vector source file. Can''t find corresponding node name "over"
in design.
---------------在源文件中找不到对应的节点“over”。
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WIN11 QUARTUS报错可能有多种原因。根据引用\[1\],如果你使用的是高于13.1版本的Quartus,那么可能会出现"modelsim executable not found"的错误。这是因为高版本的Quartus不再提供这种仿真程序,而是需要通过编程实现图形仿真。如果你使用的是13.1版本的Quartus,那么这个错误可能是因为安装时选择的位置不是预设文件夹,导致软件无法找到相应的文件。 另外,根据引用\[2\],在引入元器件时,如果Quartus将所有元件命名为"inst",会导致元器件命名重复,无法正常运行。解决方法是手动双击元件名处,给它们输入不同的名字,这样软件就可以正常编译。需要注意的是,在检查名字时,除了input/output和导线外,所有的器件都有可能出现命名错误。 此外,根据引用\[3\],如果出现"Logic function of type GND and instance 'inst' is already defined as a signal name or another logic function"的仿真报错,可能是因为接地器件(GND)的命名重复了。你可以根据报错指出的器件进行查找和修改。 综上所述,WIN11 QUARTUS报错可能是因为使用了高版本的Quartus,安装位置不正确,元器件命名重复或接地器件命名重复等原因。你可以根据具体的错误信息和引用内容提供的解决方法来解决这些问题。 #### 引用[.reference_title] - *1* *2* *3* [quartus 13.1常见报错解决方法](https://blog.csdn.net/weixin_45810064/article/details/117754811)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v91^insert_down28v1,239^v3^insert_chatgpt"}} ] [.reference_item] [ .reference_list ]
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