verilog 4位4选1多路选择器
设计代码
module mux4(
input[3:0] d0,d1,d2,d3,//4个4位的输入
input[1:0] select,//2位输入,表示选择的输入
output reg [3:0]out//4位输出,和选择的输入一致
);
always @(*) //敏感信号列表,当d0,d1,d2,d3,select任意一个改变时执行
begin
case(select)
0: out=d0;
1: out=d1;
2: out=d2;
3: out=d3;
default: out=0;
endcase
end
endmodule
仿真代码
`timescale 1ns / 100ps
module mux4text;
reg[3:0]d0;
reg[3:0]d1;
reg[3:0]d2;
reg[3:0]d3;
reg[1:0]select;
wire[3:0]out;
mux4 uut(.d0(d0),.d1(d1),.d2(d2),.d3(d3),.out(out),.select(select));
initial begin
d0 = 0;d1=0;d2=0;d3=0;
d0=0;
select = 0;
#100;
d0=1;
select = 0;
#100;
d0=2;
select = 0;
#100;
d0=3;
select = 0;
#100;
d0=4;
select = 0;
#100;
d0=5;
select = 0;
#100;
d0=6;
select = 0;
#100;
d0=7;
select = 0;
#100;
d0=8;
select = 0;
#100;
d0=9;
select = 0;
#100;
d0=10;
select = 0;
#100;
d0=11;
select = 0;
#100;
d0=12;
select = 0;
#100;
select = 0;
d0=13;
select = 0;
#100;
d0=14;
select = 0;
#100;
d0=15;
select = 0;
#100;
d1=0;
d0=0;
select = 1;
#100
d1=1;
select = 1;
#100
d1=2;
select = 1;
#100
d1=3;
select = 1;
#100
d1=4;
select = 1;
#100
d1=5;
select = 1;
#100
d1=6;
select = 1;
#100
d1=7;
select = 1;
#100
d1=8;
select = 1;
#100
d1=9;
select = 1;
#100
d1=10;
select = 1;
#100
d1=11;
select = 1;
#100
d1=12;
select = 1;
#100
d1=13;
select = 1;
#100
d1=14;
select = 1;
#100
d1=15;
select = 1;
#100
d2=0;
d1=0;
select = 2;
#100
d2=1;
select = 2;
#100
d2=2;
select = 2;
#100
d2=3;
select = 2;
#100
d2=4;
select = 2;
#100
d2=5;
select = 2;
#100
d2=6;
select = 2;
#100
d2=7;
select = 2;
#100
d2=8;
select = 2;
#100
d2=9;
select = 2;
#100
d2=10;
select = 2;
#100
d2=11;
select = 2;
#100
d2=12;
select = 2;
#100
d2=13;
select = 2;
#100
d2=14;
select = 2;
#100
d2=15;
select = 2;
#100
d3=0;
d2=0;
select = 3;
#100
d3=1;
select = 3;
#100
d3=2;
select = 3;
#100
d3=3;
select = 3;
#100
d3=4;
select = 3;
#100
d3=5;
select = 3;
#100
d3=6;
select = 3;
#100
d3=7;
select = 3;
#100
d3=8;
select = 3;
#100
d3=9;
select = 3;
#100
d3=10;
select = 3;
#100
d3=11;
select = 3;
#100
d3=12;
select = 3;
#100
d3=13;
select = 3;
#100
d3=14;
select = 3;
#100
d3=15;
select = 3;
#100
#100;
$stop;
$finish;
end
endmodule
仿真结果,使用moedlsim仿真