HDLBit: The complete timer

题链接：Exams/review2015 fancytimer - HDLBits (01xz.net)

We want to create a timer with one input that:

1. is started when a particular input pattern (1101) is detected,
2. shifts in 4 more bits to determine the duration to delay,
3. waits for the counters to finish counting, and
4. notifies the user and waits for the user to acknowledge the timer.

The serial data is available on the data input pin. When the pattern 1101 is received, the circuit must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration of the timer delay. I'll refer to this as the delay[3:0].

After that, the state machine asserts its counting output to indicate it is counting. The state machine must count for exactly (delay[3:0] + 1) * 1000 clock cycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count 6000 cycles. Also output the current remaining time. This should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for 1000 cycles. When the circuit isn't counting, the count[3:0] output is don't-care (whatever value is convenient for you to implement).

At that point, the circuit must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).

The circuit should reset into a state where it begins searching for the input sequence 1101.

Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once the 1101 and delay[3:0] have been read, the circuit no longer looks at the data input until it resumes searching after everything else is done. In this example, the circuit counts for 2000 clock cycles because the delay[3:0] value was 4'b0001. The last few cycles starts another count with delay[3:0] = 4'b1110, which will count for 15000 cycles.

  

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    
    parameter IDLE=0, R1=1, R2=2, R3=3, ENA=4, COUNTING=5, DONE=6;
    reg [2:0] state, next_state;
    reg [1:0] cnt; // 4周期延迟计数器
    reg [9:0] cnt_1000; // 1000循环计数器
    reg [3:0] delay;
    
    // 状态转移逻辑
    always @(*) begin
        case(state)
            IDLE: next_state = data ? R1:IDLE;
            R1: next_state = data ? R2:IDLE;
            R2: next_state = data ? R2:R3;
            R3: next_state = data ? ENA:IDLE;
            ENA: begin 
                if(cnt < 2'd3) 
                    next_state = ENA;
                else next_state = COUNTING;
            end
            // delay倒数至0后，还要计数1000周期再跳转，对应题中“（delay + 1）*1000”
            COUNTING: next_state = (!delay && cnt_1000==10'd999) ? DONE:COUNTING; 
            DONE: next_state = ack ? IDLE:DONE;           
            default: next_state = IDLE;
        endcase
    end
    
    always @(posedge clk) begin
        if(reset) state <= IDLE;
        else state <= next_state;
    end
    
    // 4周期延迟
    always @(posedge clk) begin
        if(state==ENA && cnt<3) cnt <= cnt+1'd1;
        else cnt <= 2'd0;
    end
    
    // counting阶段，delay倒数
    always @(posedge clk) begin
        if(state==ENA) delay <= {delay[2:0], data};
        else if(state==COUNTING && cnt_1000==10'd999) delay <= delay-1'd1;
        else delay <= delay;
    end
    
    // 每个delay的1000计数        
    always @(posedge clk) begin
        if(reset) cnt_1000 <= 10'd0;
        else if(state==COUNTING) begin
            if(cnt_1000==10'd999) cnt_1000 <= 10'd0;
        	else cnt_1000 <= cnt_1000+1'd1;
        end
        else cnt_1000 <= 10'd0;
    end
    
    assign count = delay;
    assign counting = (state==COUNTING);
    assign done = (state==DONE);
endmodule