Verilog HDL——Modelsim仿真

常用testbench语法

• $finish 和 $stop ： $finish任务用于终止仿真并跳出仿真器；$stop任务则用于中止仿真。
• `timescale [time_unit] / [time_precision] ：time_unit指定计时和延时的测量单位，time_precision则是指定仿真器的精度。
• #n ：代表延时n个时间轴单位。
• initial ：initial 块执行一次。inital 块内是顺序执行的。一般来给信号赋初值。
• always ：always表示由事件激发反复执行。

操作步骤

仿真程序仍然用上次的一个分频计数程序：

module traffic(Clk_50M, Rst, Clk30, Clk_1Hz);
input Clk_50M, Rst;
output Clk30,Clk_1Hz;


//------------分频器------------------
reg Clk_1Hz;//分频器  50M分频
reg[31:0] Cnt_1Hz;//计数
always@(posedge Clk_50M or negedge Rst)
begin
	if(!Rst)//Rst为0时  进行复位 置初值
		begin
			Cnt_1Hz <= 1;
			Clk_1Hz <= 1;
		end
	else
		begin
			if(Cnt_1Hz >= 2)//为了显示波形这里25000000临时改为2
				begin
					Cnt_1Hz <= 1;//计数器置1
					Clk_1Hz <= ~Clk_1Hz;
				end
			else
				Cnt_1Hz <= Cnt_1Hz +1;//计数
		end
end

//------------计数器------------------
reg[7:0] Cnt30;//计数器
reg Clk30;
always@(posedge Clk_1Hz or negedge Rst)
begin
	if(!Rst)
		begin
			Cnt30 <= 0;
			Clk30 <= 1;
		end
	else
		begin
			if(Cnt30 >= 30)
				begin
					Cnt30 <= 0;//计数到30清零
					Clk30 <= ~Clk30;
				end
			else
			Cnt30 <= Cnt30 + 1;
		end
end


endmodule 

这里的TestBench可以自己编写也可以使用软件自动生产的模版。

首先建立一个波形仿真文件：

然后，Edit——>Insert——>Insert Node or Bus：

选择 Run Functional Simulation：

此时工程文件下会产生simulation文件夹：

这时选择 Processing——>Start——>Start Test Bench Template Writer
simulation文件夹下的modelsim文件夹内会产生一个TestBench模板

traffic.vt文件内容：

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "05/03/2023 19:08:39"
                                                                                
// Verilog Test Bench template for design : traffic
// 
// Simulation tool : ModelSim-Altera (Verilog)
// 

`timescale 1 ps/ 1 ps
module traffic_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg Clk_50M;
reg Rst;
// wires                                               
wire Clk30;
wire Clk_1Hz;

// assign statements (if any)                          
traffic i1 (
// port map - connection between master ports and signals/registers   
	.Clk30(Clk30),
	.Clk_1Hz(Clk_1Hz),
	.Clk_50M(Clk_50M),
	.Rst(Rst)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
                                                       
// --> end                                             
$display("Running testbench");                       
end                                                    
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                                       
@eachvec;                                              
// --> end                                             
end                                                    
endmodule

这时在工程内新建一个Verilog HDL File，将traffic.vt文件内容复制进去，保存为traffic_vlg_tst.v。
然后在该模版上进行修改：

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "05/03/2023 15:40:48"
                                                                                
// Verilog Test Bench template for design : traffic
// 
// Simulation tool : ModelSim-Altera (Verilog)
// 

`timescale 1 ps/ 1 ps
module traffic_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg Clk_50M;
reg Rst;
// wires                                               
wire Clk30;
wire Clk_1Hz;

// assign statements (if any)                          
traffic i1 (
// port map - connection between master ports and signals/registers   
	.Clk30(Clk30),
	.Clk_1Hz(Clk_1Hz),
	.Clk_50M(Clk_50M),
	.Rst(Rst)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
	#0 
		Clk_50M = 0;
		Rst = 0;
	#100 
		Rst = 1;
	#8000 $stop;
// --> end                                             
$display("Running testbench");                       
end                           

always #5 Clk_50M <=~ Clk_50M;
                         
//	always                                                 
//	// optional sensitivity list                           
//	// @(event1 or event2 or .... eventn)                  
//	begin                                                  
//	// code executes for every event on sensitivity list   
//	// insert code here --> begin                          
//	always #5 Clk_50M <=~ Clk_50M;
//	@eachvec;                                              
//	// --> end                                             
//	end                                                    
endmodule

点击Assignments——>setting——>EDA Tool Settings——>Simulation

输入Test bench name，并在添加Test bench and simulation files中选中traffic_vlg_tst.v：


然后编译及运行
点击Processing——>Start Compilation，进行编译
编译完成后，点击Tools——>Run Simulation Tool——>RTL Simulation

然后可以看到仿真结果：