module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @(posedge clk)
begin
if (reset)
q<=5'h1;
else
begin
q[4] <= q[0] ^ 1'b0;
q[3] <= q[4];
q[2] <= q[0] ^ q[3];
q[1] <= q[2];
q[0] <= q[1];
end
end
endmodule
Lfsr5_hdlbits
最新推荐文章于 2024-03-17 21:42:11 发布