module top_module();
reg clk,in,out;
reg [2:0] s;
always #5 clk = ~clk;
initial
begin
clk = 0;
in = 0;
s = 3'h2;
#10 s=3'h6;
#10 s=3'h2;in=1;
#10 in = 0;s=3'h7;
#10 in =1;s=3'h0;
#30 in = 0;
end
q7 inst1(
.clk(clk),
.in(in),
.s(s),
.out(out)
);
endmodule
hdlbits_tb2
最新推荐文章于 2022-04-18 11:30:00 发布