HDLBits练习——Exams/2014 q4b

Consider the n-bit shift register circuit shown below:

Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.

Connect the R inputs to the SW switches,clk to KEY[0],E to KEY[1],L to KEY[2], and w to KEY[3]. Connect the outputs to the red lights LEDR[3:0].
(Reuse your MUXDFF from exams/2014_q4a.)

---

前言

两个输入，包括一个复合控制信号KEY，一个输入信号SW；一个输出信号LEDR。

代码

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); 
    MUXDFF instance1(KEY[0],KEY[1],KEY[2],KEY[3],SW[3],LEDR[3]);
    MUXDFF instance2(KEY[0],KEY[1],KEY[2],LEDR[3],SW[2],LEDR[2]);
    MUXDFF instance3(KEY[0],KEY[1],KEY[2],LEDR[2],SW[1],LEDR[1]);
    MUXDFF instance4(KEY[0],KEY[1],KEY[2],LEDR[1],SW[0],LEDR[0]);    
endmodule
module MUXDFF(input clk,E,L,w,R,output Q);
    always@(posedge clk)begin
        Q<=L?R:E?w:Q;
    end
endmodule

总结

例化四个MUXDFF模块，第一个例化的w位输入KEY[3]，其余的w位输入前一位的输出值。