模N计数器的Verilog HDL代码

//计数器位数：NBITS
//模数：UPTO
module ModuloN_Cntr(Clock, Clear, Q, QBAR);

parameter NBITS = 2, UPTO = 3;
input Clock, Clear;
output [NBITS-1:0]Q, QBAR;
reg [NBITS-1:0]Counter;

always @(posedge Clock)
  if(Clear)
    Counter <= 0;
  else
    Counter <= (Counter + 1) % UPTO;
  assign Q = Counter;
  assign QBAR = ~ Counter;

endmodule