2、VHDL的STD_LOGIC_ARITH包常见数据类型转换

(1)、CONV_STD_LOGIC_VECTOR(p,b)：将数据类型integer、unsigned、signed、std_logic的操作符转换成位宽为b的std_logic_vector

例:integer转换成std_logic_vector

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
USE IEEE.STD_LOGIC_ARITH.all;


ENTITY data IS
    PORT(
       a : IN  INTEGER(7 downto 0);
       b : IN  INTEGER(7 downto 0);
       c : OUT STD_LOGIC_VECTOR(7 downto 0)
        
     );

END ENTITY;

ARCHITECTURE rtl OF data IS
BEGIN
   
    c <= CONV_STD_LOGIC_VECTOR((a+b),8);

END rtl;

例:std_logic转换成std_logic_vector

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
USE IEEE.STD_LOGIC_ARITH.all;


ENTITY data IS
    PORT(
       a : IN  STD_LOGIC;
       c : OUT STD_LOGIC_VECTOR(7 downto 0)   
     );

END ENTITY;

ARCHITECTURE rtl OF data IS
BEGIN
   
    c <= CONV_STD_LOGIC_VECTOR(a,8);

END rtl;

(2)、conv_integer(p)：将数据类型为integer,unsigned,signed,std_logic或std_ulogic的操作数p转换成integer类型，不包括std_logic_vector。

例:std_logic转换成integer

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
USE IEEE.STD_LOGIC_ARITH.all;


ENTITY data IS
    PORT(
       a : IN  STD_LOGIC;
       c : OUT INTEGER  
     );

END ENTITY;

ARCHITECTURE rtl OF data IS
BEGIN
   
    c <= CONV_INTER(a);

END rtl;

(3)、conv_unsigned(p,b):将数据类型为integer,signed,std_logic或std_ulogic的操作数p转换成宽度为b的unsigned的数据类型

例:std_logic转换成unsigned

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
USE IEEE.STD_LOGIC_ARITH.all;


ENTITY data IS
    PORT(
       a : IN  STD_LOGIC;
       c : OUT UNSIGNED(7 DOWNTO 0) 
     );

END ENTITY;

ARCHITECTURE rtl OF data IS
BEGIN
   
    c <= CONV_UNSIGNED(a,8);

END rtl;

(4)、conv_signed(p,b):将数据类型为integer,unsigned,std_logic或std_ulogic的操作数p转换成宽度为b的signed的数据类型

例:std_logic转换成signed

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
USE IEEE.STD_LOGIC_ARITH.all;


ENTITY data IS
    PORT(
       a : IN  STD_LOGIC;
       c : OUT SIGNED(7 DOWNTO 0) 
     );

END ENTITY;

ARCHITECTURE rtl OF data IS
BEGIN
   
    c <= CONV_SIGNED(a,8);

END rtl;