lattice unconnected pin, preventing the optimization during synthesis

最新推荐文章于 2024-04-15 20:15:08 发布

beetleinv

最新推荐文章于 2024-04-15 20:15:08 发布

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分类专栏： FPGA/CPLD 文章标签： verilog

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What is the procedure to prevent unused IO logic from getting optimized out during Synthesis and MAP in Lattice Diamond, while using GUI or Active-HDL batch mode?
Lattice Diamond tool prevents unused, unconnected IO logic from getting generated, but sometimes user might want to keep a particular IO assignment and the related logic.

Below is the procedure to prevent unwanted optimization:

add the following attributes for preventing the optimization during synthesis to your source code:

e.g. input clk, rst, test / synthesis syn_force_pads=1 syn_noprune=1/;**

In the Lattice Diamond active Strategy, go to MAP> Design > command line options >add “-u”

This argument will prohibit Mapper from removing unused logic.

For Active-HDL batch mode:

There is a check box in the Mapper window called \u201Cremove unused logic\u201D. Unchecking this box will add “-u” to your mapper command line options resulting in the \u201C-s 5 -o\u201D section of the mapper command line arguments being changed to \u201C-s 5 \u2013u -o\u201D. This will let the user keep unused IO logic.