irun简单的仿真环境

编写一个irun的Makefile，用来仿真Verilog，适合编写小的模块。

run:
	irun +sv +nc64bit -access +rwc +nctimescale+1ns/1ps -loadpli1 debpli:novas_pli_boot -f file.lst -l irun_rtl.log
verdi:
	verdi -f file.lst +incdir+./ -ssf wave.fsdb &
clean:
	rm -rf INCA* *.log *.txt coverage_DB

其中 -loadpli1 debpli:novas_pli_boot是在centos6中需要添加的，我的系统是64位，查看linux系统的命令是

getconf LONG_BIT

export PATH=$VERDI_HOME/share/PLI/IUS/LINUX64/boot:$PATH
export PATH=$VERDI_HOME/share/PLI/lib/LINUX64:$PATH

module TB (/*AUTOARG*/) ;

   reg rst_n;
   reg clk;
   reg [7:0] addr;
   reg 	     wen;
   reg [11:0] data;
   /*autowire*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire			clk_o;			// From func_top of func_top.v
   wire [11:0]		data_o;			// From func_top of func_top.v
   // End of automatics
   func_top func_top(/*autoinst*/
		     // Outputs
		     .data_o		(data_o[11:0]),
		     .clk_o		(clk_o),
		     // Inputs
		     .clk		(clk),
		     .rst_n		(rst_n),
		     .addr		(addr[7:0]),
		     .wen		(wen),
		     .data		(data[11:0]));
   
initial
begin
       clk=1'b0;
       rst_n=1'b1;
       #10
       rst_n=1'b0;
       #500
       rst_n=1'b1;
end

   always  begin
      #5 clk=~clk;
   end
   int i;
   
initial
  begin
      #800
   for( i=0;i<34;i++)begin
      @(posedge clk)begin
	 addr =i;
	 wen=1;
	 data=i+50;
      end
      @(posedge clk)begin
	 addr =i;
	 wen=0;
	 data=i;
      end	
   end // for (int i=0;i<34;i++)

      for(int i=0;i<34;i++)begin
      @(posedge clk)begin
	 addr =i+8'b0100_0000;
	 wen=1;
	 data=i+20;
      end
      @(posedge clk)begin
	 addr =i+8'b0100_0000;
	 wen=0;
	 data=i;
      end	
      end // for (int i=0;i<34;i++)
   //ch_num
       @(posedge clk)begin
	 addr =8'b1100_0000;
	 wen=1;
	 data=20;
      end
      @(posedge clk)begin
	 addr =i+8'b1100_0000;
	 wen=0;
	 data=i;
      end
  //start
       @(posedge clk)begin
	 addr =8'b1100_0001;
	 wen=1;
	 data=20;
      end
      @(posedge clk)begin
	  addr =8'b1100_0001;
	 wen=0;
	 data=i;
      end  
   #100us;
   
  //stop
       @(posedge clk)begin
	 addr =8'b1100_0010;
	 wen=1;
	 data=20;
      end
      @(posedge clk)begin
	 addr =8'b1100_0010;
	 wen=0;
	 data=i;
      end
  # 1us;
$finish;//如果是$stop结尾，则会进入ncsim
 end
  
initial
  begin
     $fsdbDumpfile("wave.fsdb");
     $fsdbDumpvars(0,TB);
     forever #1us $fsdbDumpflush();
  end

   
endmodule // TB