FPGA Verilog 信号的上升沿、下降沿检测

module edge_check (
        input                           clk,            //时钟信号
        input                           signal,         //输入信号
        output                          pos_edg,        //输出是否为上升沿
        output                          neg_edg         //输出是否为下降沿
    );

    reg signal_reg0;
    reg signal_reg1;

    always @ (posedge clk) begin
        signal_reg0     <= signal;
        signal_reg1     <= signal_reg0;
    end

    assign pos_edg = !signal_reg1 && signal_reg0;
    assign neg_edg = signal_reg1 && !signal_reg0;

endmodule