module Syn_DFF(clk, rst_n,Din,Dout);
input clk,rst_n,Din;
output Dout;
reg Dout;
always@(posedge clk)
begin
if(!rst_n)
Dout <= 1'b0;
else
Dout <= Din;
end
endmodule
module Asyn_DFF(clk, rst_n,Din,Dout);
input clk,rst_n,Din;
output Dout;
reg Dout;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
Dout <= 1'b0;
else
Dout <= Din;
end
endmodule
set_multicycle_path-from[get_cells UFF0]-to[get_cells UFF1]-hold-end 2
错误