Verilog 带符号的数值运算 乘法器

wire [3:0] dataA = 4'hF;
wire signed [3:0] dataB = -1;

wire [7:0] r01;
wire [7:0] r02;
wire [7:0] r03;	
wire [7:0] r11;
wire [7:0] r12;
wire [7:0] r13;
wire [7:0] r21;
wire [7:0] r22;
wire [7:0] r23;

//1：乘法符号的乘法，根据数据类型来选择乘法器类型，如果A和B都是符号数，则乘法器为带符号乘法器
assign r01 = dataA * dataA;   //8'b1110 0001
assign r02 = dataA * dataB;   //8'b1110 0001
assign r03 = dataB * dataB;   //8'b1	

//2：无符号4位乘法器，将数据转化为无符号数，然后相乘
Mult_unsigned	Mult_unsigned_inst1 (
	.dataa ( dataA ),
	.datab ( dataA ),
	.result ( r11 )				//8'b1110 0001
	);

Mult_unsigned	Mult_unsigned_inst2 (
	.dataa ( dataA ),
	.datab ( dataB ),
	.result ( r12 )				//8'b1110 0001
	);

Mult_unsigned	Mult_unsigned_inst3 (
	.dataa ( dataB ),
	.datab ( dataB ),
	.result ( r13 )				//8'b1110 0001
	);	


//3：有符号4位乘法器，将数据转化为符号数，然后相乘
Mult_signed1	Mult_signed1_inst1 (
	.dataa ( dataA ),
	.datab ( dataA ),
	.result ( r21 )				//20'b1	
	);
	
Mult_signed1	Mult_signed1_inst2 (
	.dataa ( dataA ),
	.datab ( dataB ),
	.result ( r22 )				//20'b1	
	);

Mult_signed1	Mult_signed1_inst3 (
	.dataa ( dataB ),
	.datab ( dataB ),
	.result ( r23 )				//20'b1	
	);

 

乘法器长度大于乘数的情况

wire [3:0] dataA = 4'hF;
wire signed [3:0] dataB = -1;

wire [11:0] r01;
wire [11:0] r02;
wire [11:0] r03;	
wire [11:0] r11;
wire [11:0] r12;
wire [11:0] r13;
wire [11:0] r21;
wire [11:0] r22;
wire [11:0] r23;

//1：乘法符号的乘法，根据数据类型来选择乘法器类型，如果A和B都是符号数，则乘法器为带符号乘法器
assign r01 = dataA * dataA;   //11'b0000_1110 0001
assign r02 = dataA * dataB;   //11'b0000_1110 0001
assign r03 = dataB * dataB;   //11'b1	

//2：无符号6位乘法器，将数据转化为无符号数，然后相乘
Mult_unsigned	Mult_unsigned_inst1 (
	.dataa ( dataA ),
	.datab ( dataA ),
	.result ( r11 )				//11'b0000_1110 0001
	);

Mult_unsigned	Mult_unsigned_inst2 (
	.dataa ( dataA ),
	.datab ( dataB ),
	.result ( r12 )				//11'b0000_1110 0001
	);

Mult_unsigned	Mult_unsigned_inst3 (
	.dataa ( dataB ),
	.datab ( dataB ),
	.result ( r13 )				//11'b0000_1110 0001
	);	


//3：有符号6位乘法器，将数据转化为符号数，然后相乘
Mult_signed1	Mult_signed1_inst1 (
	.dataa ( dataA ),
	.datab ( dataA ),
	.result ( r21 )				//11'b0000_1110 0001
	);
	
Mult_signed1	Mult_signed1_inst2 (
	.dataa ( dataA ),
	.datab ( dataB ),
	.result ( r22 )				//11'b0000_1110 0001
	);

Mult_signed1	Mult_signed1_inst3 (
	.dataa ( dataB ),
	.datab ( dataB ),
	.result ( r23 )				//11'b0000_1110 0001
	);

结论

1：quartus的IP核中的乘法器的长度大于乘数的情况下，先将乘数高位补0，然后将乘数转化成为符号数或者无符号数，最后对将乘数相乘